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440GX – Power PC 440GX Embedded Processor
AMCC
13
Revision 1.15 – August 30, 2007
Data Sheet
External master interface
- Write posting from external master
- Read prefetching on PLB for external master reads
- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
Ethernet Controller Interface
Ethernet support provided by the PPC440GX interfaces to the physical layer, but the PHY is not included on the
chip.
Features include:
One to four 10/100 interfaces running in full- and half-duplex modes
- One full Media Independent Interface (MII) with 4-bit parallel data transfer
- Two Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer
- Four Serial Media Independent Interfaces (SMII)
One or two GMII interfaces running in full- and half-duplex modes at 10Mb/s or 100Mb/s or 1000Mb/s
- One full Gigabit Media Independent Interface (GMII) with 8-bit parallel data transfer
- Two Reduced Gigabit Media Independent Interfaces (RGMII) with 4-bit parallel data transfer
One or two TBI interfaces running in full- and half-duplex modes at 10Mb/s or 100Mb/s or 1000Mb/s
- One full Ten Bit Interface (TBI) with 10-bit parallel data transfer
- Two Reduced Ten Bit Interfaces (RTBI) with 4-bit parallel data transfer
Jumbo frame support (9016 byte)
- Support for Ethernet II formatted frames (RFC894)
- Support for IEEE formatted frames (RFC1042)
- Handles VLAN-tagged frames
TCP/IP Acceleration Hardware (TAH)
Features include:
Offloads Gigabit Ethernet protocol processing from the CPU
Checksum verification for TCP/UDP/IP headers in the receive path
Checksum generation for TCP/UDP/IP headers in the transmit path
TCP segmentation support in the transmit path
DMA Controller
Features include:
Supports the following transfers:
- Memory-to-memory transfers
- Buffered peripheral to memory transfers
- Buffered memory to peripheral transfers
Four channels
Scatter/Gather capability for programming multiple DMA operations
8-, 16-, 32-bit peripheral support (OPB and external)
64-bit addressing
128 byte FIFO buffer
Address increment or decrement
Supports internal and external peripherals
Support for memory mapped peripherals