- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368096 > PPC440EP-3pbfffCx (Applied Micro Circuits Corp.) Power PC 440EP Embedded Processor PDF資料下載
參數(shù)資料
| 型號： | PPC440EP-3pbfffCx |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Power PC 440EP Embedded Processor |
| 中文描述： | 440EP的Power PC嵌入式處理器 |
| 文件頁數(shù)： | 56/84頁 |
| 文件大?。?/td> | 541K |
| 代理商： | PPC440EP-3PBFFFCX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁當(dāng)前第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
56
AMCC Proprietary
440EP – PPC440EP Embedded Processor
Revision 1.26 – April 25, 2007
Data Sheet
NAND Flash Interface
NFALE
Address Latch Enable.
O
Multiplex
NFCE0:3
Chip Enable (
multiplexed with the
PerCS0:3
signals)
.
O
Multiplex
NFCLE
Command Latch Enable.
O
Multiplex
NFRdyBusy
Ready/Busy.
Indicates status of device during program erase or page read.
This signal is wire-or connected from all NAND Flash devices.
I
Multiplex
NFREn
Read Enable strobe.
O
Multiplex
NFWEn
Write Enable strobe.
O
Multiplex
Serial Peripheral Interface
SCPClkOut
Clock output.
SCPClkOut, the serial port master clock out, is used to
synchronize all data movement both into and out of the device
through the serial data ports. Normally, data is shifted out on
the rising edge of the clock and shifted in on the negative
edge.
SCPClkOut is also used to shift data into and out of the slave
device. When the SPMODE register is reset, SCPClkOut is
forced to 0.
O
3.3V LVTTL
SCPDI
Data In.
Data is received from the connected slave device and is
captured synchronously with SysClk.
I
3.3V LVTTL
SCPDO
Data output.
Data is sent to the connected slave device synchronously with
SysClk.
O
3.3V LVTTL
Interrupts Interface
IRQ0:4
External interrupt requests 0 through 4.
I/O
3.3V LVTTL
1, 5
IRQ5
External interrupt request 5.
I
3.3V tolerant
2.5V CMOS
1
IRQ6:9
External interrupt requests 6 through 9.
I/O
3.3V LVTTL
1
JTAG Interface
TCK
Test Clock.
I
3.3V LVTTL
w/pull-up
1
TDI
Test Data In.
I
3.3V LVTTL
w/pull-up
4
TDO
Test Data Out.
O
3.3V LVTTL
TMS
Test Mode Select.
I
3.3V LVTTL
w/pull-up
1
TRST
Test Reset.
I
3.3V LVTTL
w/pull-up
5
Table 6. Signal Functional Description (Sheet 7 of 9)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω
to 3.3V
)
3. Must pull down (recommended value is 1k
Ω
)
4. If not used, must pull up (recommended value is 3k
Ω
to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω
)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC440GP-3CC333C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400C | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400CZ | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400E | Power PC 440GP Embedded Processor |
| PPC440GP-3CC400EZ | Power PC 440GP Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC440EP-5JC333 | 制造商:AppliedMicro 功能描述: |
| PPC440EPX-NPAFFFTS | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerPC 440EPx Embedded Processor |
| PPC440EPX-NTA400E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
| PPC440EPX-NTA400EZ | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Tape and Reel |
| PPC440EPX-NTA533E | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 667 MHZ, 2 10/100/1000 ETHERNET, - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。