- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368095 > PPC405GP-3FE200CZ (APPLIEDMICRO INC) Power PC 405GP Embedded Processor PDF資料下載
參數(shù)資料
| 型號： | PPC405GP-3FE200CZ |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Power PC 405GP Embedded Processor |
| 中文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA456 |
| 封裝： | 35 X 35 MM, PLASTIC, LEAD FREE, EBGA-456 |
| 文件頁數(shù)： | 56/59頁 |
| 文件大小： | 782K |
| 代理商： | PPC405GP-3FE200CZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁當(dāng)前第56頁第57頁第58頁第59頁
405GP – Power PC 405GP Embedded Processor
56
AMCC
Revision 2.03 – September 7, 2007
Data Sheet
PCI Divider from PLB
2, 3
D18/A20
GPIO1[TS1E]
0
0
1
1
K25/K20
EMCTxErr
0
0
1
1
C20/C19
GPIO2[TS2E]
0
1
0
1
K23/J21
EMCTxEn
0
1
0
1
AD2/N7
UART1_RTS
/
UART1_DTR
0
1
0
1
Divide by 1
Divide by 2
Divide by 3
Divide by 4
External Bus Divider from PLB
2
Divide by 2
Divide by 3
Divide by 4
Divide by 5
ROM Width
AC2/N3
UART1_Tx
8-bit ROM
16-bit ROM
32-bit ROM
Reserved
0
0
1
1
ROM Location
U2/P4
HoldAck
0
1
Y3/U4
ExtAck
0
1
AF18/AB18
GPIO4[TS2O]
0
1
PPC405GP Peripheral Attach
PPC405GP PCI Attach
PCI Asynchronous Mode Enable
Synchronous PCI Mode
Asynchronous Mode
PCI Arbiter Enable
3
Internal Arbiter Disabled
Internal Arbiter Enabled
Note:
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the
PPC405GP. These bits are shown for information only; and do not require modification except in special clocking circumstances such as
spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GP, visit the technical
documents area of the AMCC PowerPC web site.
2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in “Clocking
Specifications” on page 47. Further requirements are detailed in the Clocking chapter of the
PowerPC 405GP Embedded Processor
User’s Manual
.
3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by using
three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
PPC405GP Strapping Pin Assignments
(Part 2 of 2)
Function
Option
Ball Strapping
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC405GP-3FE266C | Power PC 405GP Embedded Processor |
| PPC405GP-3FE266CZ | Power PC 405GP Embedded Processor |
| PPC405GPR-3KB400Z | Power PC 405GPr Embedded Processor |
| PPC405GPR-3BB266 | Power PC 405GPr Embedded Processor |
| PPC405GPR-3BB266Z | Power PC 405GPr Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC405GP-3FE266C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor |
| PPC405GP-3FE266CZ | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 266MHz 3.3V 456-Pin EBGA T/R |
| PPC405GP-3KE133C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor |
| PPC405GP-3KE133CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor |
| PPC405GP-3KE200C | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。