參數(shù)資料
型號(hào)： PPC405GP-3EE266C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： Power PC 405GP Embedded Processor
中文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA413
封裝： 25 X 25 MM, PLASTIC, EBGA-413
文件頁數(shù)： 55/59頁
文件大?。?/td> 782K
代理商： PPC405GP-3EE266C
405GP – Power PC 405GP Embedded Processor
AMCC
55
Revision 2.03 – September 7, 2007
Data Sheet
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to
enable default initial conditions prior to PPC405GP start-up. The actual capture instant is the nearest SysClk edge
before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down
(logical 0) resistors to select the desired default conditions. The recommended pull-up is 3k
Ω
to +3.3V or 10k
Ω
to
+5V. The recommended pull-down is 1K
Ω
to GND. These pins are use for strap functions only during reset. They
are used for other signals during normal operation. The following table lists the strapping pins along with their
functions and strapping options. The pin for the 456-ball package is listed first (for example, AF3), followed by the
corresponding pin for the 413-ball package (for example, U8), which appears as AF3/U8. The signal names
assigned to the pins for normal operation follow the pin numbers.
PPC405GP Strapping Pin Assignments
(Part 1 of 2)
Function
Option
Ball Strapping
AF2/T8
UART0_DTR
PLL Tuning
1
for 6
≤
M
≤
7 use choice 3
for 7 < M
≤
12 use choice 5
for 12 < M
≤
32 use choice 6
AF3/U8
UART0_Tx
0
0
0
0
1
1
1
1
D16/A17
DMAAck0
0
0
1
1
B14/A15
DMAAck2
0
0
1
1
P25/R23
EMCTxD3
0
0
1
1
L25/K21
EMCTxD1
0
0
1
1
AD16/AB15
UART0_RTS
0
1
0
1
0
1
0
1
Choice 1; TUNE[5:0] = 010001
Choice 2; TUNE[5:0] = 111011
Choice 3; TUNE[5:0] = 010011
Choice 4; TUNE[5:0] = 111101
Choice 5; TUNE[5:0] = 010101
Choice 6; TUNE[5:0] = 010110
Choice 7; TUNE[5:0] = 111110
Choice 8; TUNE[5:0] = 100100
0
0
1
1
0
0
1
1
PLL Forward Divider
2
B15/B14
DMAAck1
0
1
0
1
C12/A8
DMAAck3
0
1
0
1
L24/J22
EMCTxD2
0
1
0
1
J26/F22
EMCTxD0
0
1
0
1
Bypass mode
Divide by 3
Divide by 4
Divide by 6
PLL Feedback Divider
2
Divide by 1
Divide by 2
Divide by 3
Divide by 4
PLB Divider from CPU
2
Divide by 1
Divide by 2
Divide by 3
Divide by 4
OPB Divider from PLB
2
Divide by 1
Divide by 2
Divide by 3
Divide by 4
相關(guān)PDF資料
PDF描述
PPC405GP-3EE266CZ Power PC 405GP Embedded Processor
PPC405GP-3FE133C Power PC 405GP Embedded Processor
PPC405GP-3FE133CZ Power PC 405GP Embedded Processor
PPC405GP-3FE200C Power PC 405GP Embedded Processor
PPC405GP-3FE200CZ Power PC 405GP Embedded Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC405GP-3EE266CZ 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor
PPC405GP-3FE133C 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32BIT 0.25UM 133MHZ 3.3V 456PIN EBGA - Trays
PPC405GP-3FE133CZ 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor
PPC405GP-3FE200C 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA Tray
PPC405GP-3FE200CZ 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA T/R
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