參數(shù)資料
型號: PPC405EX-SpAfffTx
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 405EX Embedded Processor
中文描述: 嵌入式處理器的PowerPC 405EX
文件頁數(shù): 62/67頁
文件大?。?/td> 457K
代理商: PPC405EX-SPAFFFTX
PPC405EX – PowerPC 405EX Embedded Processor
62
AMCC Proprietary
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
Figure 8. DDR SDRAM Read Data Path
DDR SDRAM Read Cycle Timing
The following diagram illustrates the relationship of the signals involved with a DDR read operation.
Figure 9. DDR SDRAM Memory Data and DQS
PLB bus
[0:63]
DQ
Data
(x32)
Programmed
Read DQS
Delay
Package
pins
Mux
C
D
FF: Flip-Flop
Q2
DQS
DDR 1X Clock
Mux
(x32)
(x32)
Read FIFO
PLB 1X Clock
Stage 2
Stage 1
Stage 3
FF
PLB bus
[64:127]
DQS Rising
Edge Sync
DQS Falling
Edge Sync
Q3
0
2
6
4
Coarse Delay
Cycles
Delay
Driver
Rec
MemDCFdbkD
MemDCFdbkR
Ext FeedBack
Signals
Read Start
Feedback
Data Capture
Window
DDR 1X Clock
Stage 2 Store
Oversampling
DQS aligned
FBK signal
CAS Lat Delay
FeedBack
Signal Gen
Fine Delay
T1 T2 T3 T4
Fine Delay
FF
FF
7
5
3
1
1
0
7
Upper
Lower
FF
Q2_Ovs
FF
+1
Compare
DDR 1X Clock
Oversampling
Clock
Read Latency adjust circuit
C
D
FF
FF
adjust
DQS
MemData
T
SD
T
HD
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