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參數(shù)資料
| 型號： | PPC405EX-SpAfffTx |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 405EX Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 405EX |
| 文件頁數(shù)： | 41/67頁 |
| 文件大小： | 457K |
| 代理商： | PPC405EX-SPAFFFTX |
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PPC405EX – PowerPC 405EX Embedded Processor
Revision 1.09 - August 21, 2007
AMCC Proprietary
41
Preliminary Data Sheet
External Peripheral Interface
PerAddr05:31
Address bus 5:31.
I/O
3.3V LVTTL
PerClk
Clock output.
O
3.3V LVTTL
PerCS0
Chip selects 0.
O
3.3V LVTTL
2
PerCS1:3
Chip selects 1:3.
I/O
3.3V LVTTL
1, 2
PerData00:31
Data bus 0:31.
I/O
3.3V LVTTL
PerDataPar0:3
Data bus parity 0:3.
I/O
3.3V LVTTL
PerOE
Output enable.
O
3.3V LVTTL
2
PerReady
Slave is ready to trasfer data.
I
3.3V LVTTL
receiver
PerBLast
Last transfer of burst access.
I/O
3.3V LVTTL
1, 4
PerErr
External bus error.
I/O
3.3V LVTTL
1, 5
PerRW
Read/Write.
I/O
3.3V LVTTL
1, 2
PerWBE0:3
Write Byte enable 0:3.
I/O
3.3V LVTTL
1, 2
ExtReset
External reset.
O
3.3V LVTTL
External Bus Master Interface
BusReq
External bus request.
I/O
3.3V LVTTL
1
ExtAck
External data transfer complete.
I/O
3.3V LVTTL
1
ExtReq
External data transfer request.
I/O
3.3V LVTTL
1, 4
HoldReq
External request for bus access.
I/O
3.3V LVTTL
1, 5
HoldAck
External request acknowledge.
I/O
3.3V LVTTL
1
DMA Interface
DMAAck0:1
External peripheral DMA acknowledge.
I/O
3.3V LVTTL
DMAAck2:3
External peripheral DMA acknowledge.
I/O
3.3V LVTTL
1
DMAReq0:1
External peripheral DMA request.
I/O
3.3V LVTTL
5
DMAReq2
External peripheral DMA request.
I/O
3.3V LVTTL
1, 5
DMAReq3
External peripheral DMA request.
I/O
3.3V LVTTL
5
DMAEOT0:1
External DMA peripheral end-of-transmission.
I/O
3.3V LVTTL
5
DMAEOT2:3
External DMA peripheral end-of-transmission.
I/O
3.3V LVTTL
1, 5
Table 6. Signal Functional Description (Sheet 4 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
相關PDF資料 |
PDF描述 |
|---|---|
| PPC405EZ-CSAfffTx | PowerPC 405EZ Embedded Processor |
| PPC405GP-3BE133C | Power PC 405GP Embedded Processor |
| PPC405GP-3KE133C | Power PC 405GP Embedded Processor |
| PPC405GP-3KE133CZ | Power PC 405GP Embedded Processor |
| PPC405GP-3KE200C | Power PC 405GP Embedded Processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PPC405EX-SPD400T | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 600 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays |
| PPC405EX-SPD533T | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 600 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays |
| PPC405EX-SPD600T | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 600 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays |
| PPC405EX-SSA333T | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 533 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays |
| PPC405EX-SSA400T | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 533 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays |
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