參數(shù)資料
型號(hào)： PPC405EP-3GB266C
廠商： APPLIEDMICRO INC
元件分類： 微控制器/微處理器
英文描述： PowerPC 405EP Embedded Processor
中文描述： 32-BIT, 266.66 MHz, RISC PROCESSOR, PBGA385
封裝： 31 X 31 MM, PLASTIC, EBGA-385
文件頁數(shù)： 33/50頁
文件大?。?/td> 373K
代理商： PPC405EP-3GB266C
PPC405EP – PowerPC 405EP Embedded Processor
Revision 1.07 – September 10, 2007
Data Sheet
AMCC
33
SDRAM Interface
MemData00:31
Memory data bus.
Notes:
1. MemData00 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
I/O
3.3V LVTTL
MemAddr12:00
Memory address bus.
Notes:
1. MemAddr12 is the most significant bit (msb).
2. MemAddr00 is the least significant bit (lsb).
O
3.3V LVTTL
BA1:0
Bank Address supporting up to 4 internal banks.
O
3.3V LVTTL
RAS
Row Address Strobe.
O
3.3V LVTTL
CAS
Column Address Strobe.
O
3.3V LVTTL
DQM0:3
DQM for byte lane: 0 (MemData00:7),
1 (MemData08:15),
2 (MemData16:23), and
3 (MemData24:31)
O
3.3V LVTTL
BankSel0:1
Select up to two external SDRAM banks.
O
3.3V LVTTL
WE
Write Enable.
O
3.3V LVTTL
ClkEn0:1
SDRAM Clock Enable.
O
3.3V LVTTL
MemClkOut0:1
Two copies of an SDRAM clock allows, in some cases, glueless
SDRAM attach without requiring this signal to be repowered by a PLL
or zero-delay buffer.
O
3.3V LVTTL
External Slave Peripheral Interface
PerData00:15
Peripheral data bus.
Note:
PerData00 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerAddr03:05
PerAddr06:31
Peripheral address bus.
Note:
PerAddr03 is the most significant bit (msb) on this bus.
I/O
5V tolerant
3.3V LVTTL
1
PerWBE0:1
These pins act as byte-enables which are valid for an entire cycle or
as write-byte-enables which are valid for each byte on each data
transfer, allowing partial word transactions.
O
5V tolerant
3.3V LVTTL
7
[PerWE]
Peripheral write enable. Low when either of the two PerWBE0:1 write
byte enables are low.
To access this function, software must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
PerCS0
Peripheral chip select bank 0.
O
5V tolerant
3.3V LVTTL
7
[PerCS1:4]
Four additional peripheral chip selects
To access this function, software must toggle a DCR bit.
O
5V tolerant
3.3V LVTTL
1, 7
PerOE
Peripheral output enable.
O
5V tolerant
3.3V LVTTL
7
PerR/W
Peripheral read/write. High indicates a read from memory, low
indicates a write to memory.
O
5V tolerant
3.3V LVTTL
Table 6. Signal Functional Description (Sheet 3 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料
PDF描述
PPC405EP-3GB266CZ PowerPC 405EP Embedded Processor
PPC405EP-3GB333C PowerPC 405EP Embedded Processor
PPC405EP-3GB333CZ PowerPC 405EP Embedded Processor
PPC405EP-3LB133C PowerPC 405EP Embedded Processor
PPC405EP-3LB133CZ PowerPC 405EP Embedded Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PPC405EP-3GB266CZ 制造商:AppliedMicro 功能描述:MPU 405EP RISC 32-Bit 0.18um 266MHz 3.3V 385-Pin EBGA T/R
PPC405EP-3GB333C 制造商:AppliedMicro 功能描述:MPU 405EP RISC 32-Bit 0.18um 333MHz 3.3V 385-Pin EBGA Tray 制造商:AMCC 功能描述:MPU 405EP RISC 32BIT 0.18UM 333MHZ 3.3V 385PIN EBGA - Trays
PPC405EP-3GB333CZ 制造商:AppliedMicro 功能描述:MPU 405EP RISC 32-Bit 0.18um 333MHz 3.3V 385-Pin EBGA T/R
PPC405EP-3LB133C 制造商:AppliedMicro 功能描述:MPU 405EP RISC 32-Bit 0.18um 133MHz 3.3V 385-Pin EBGA Tray 制造商:AMCC 功能描述:MPU 405EP RISC 32BIT 0.18UM 133MHZ 3.3V 385PIN EBGA - Trays 制造商:AMCC 功能描述:AMCPPC405EP-3LB133C 32 Bit PowerPC
PPC405EP-3LB133CZ 制造商:AppliedMicro 功能描述:MPU 405EP RISC 32-Bit 0.18um 133MHz 3.3V 385-Pin EBGA T/R
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