參數(shù)資料
型號(hào)： PPC403GC-JA40C1
元件分類： 32位微控制器
英文描述： 32-Bit Microprocessor
中文描述： 32位微處理器
文件頁數(shù)： 35/48頁
文件大?。?/td> 768K
代理商： PPC403GC-JA40C1
IBM PowerPC 403GC
35
SRAM, ROM, or I/O Read Request, Wait Extended with Ready
Bank Register Bit Settings
Notes:
1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword.
2. See Table 19 on page 32 for WBE signal definitions based on bus width.
3. WBE signals can be read/write byte enables based on the setting of a control bit in the IOCR. See waveform and
note 3 on page 33.
4. Wait must be programmed to a value
≥
(CSon + OEon). If Wait > (CSon + OEon), then all signals will retain the
values shown in cycle 4 until the Wait timer expires.
5. If Hold is programmed > 001, all 403GC output signals retain the values shown in cycle 7 until the Hold timer
expires.
6. If Wait = 00 0000, the Ready input is ignored and single-cycle transfers occur. If Wait = 00 0001, Ready is sampled
starting in cycle 2. If Wait > 00 0001, Ready is sampled starting after the Wait cycles have expired.
7. The Ready input can be synchronous or asynchronous based on the setting of a control bit in the IOCR. When
Ready is synchronous, data is captured one cycle after Ready is sampled active. When Ready is asynchronous,
data is transferred in the third cycle after Ready is sampled active.
8. If the Ready input has not been sampled active within 128 cycles from the start of the bus operation, and the
device-paced timeout disable in the IOCR is not set to one, the operation will terminate and a timeout error will
occur.
SLF
Burst
Mode
Bus
Width
Ready
Enable
Wait
States
CSon
OEon
WEon
WEoff
Hold
Bit 13
Bit 14
Bits 15:16
Bit 17
Bits 18:23
Bit 24
Bit 25
Bit 26
Bit 27
Bits 28:30
0 or 1
0
xx
1
00 0010
0 or 1
0 or 1
0 or 1
x
001
A6:29,
1
WBE2[A30],
WBE3[A31]
R/W
CSx
5
OE
4,5
WBE0:3
2,3
D0:31
Address Valid
Data In
CSon=0
CSon=1
CSon=0
OEon=0
CSon=0,1
OEon=1,0
CSon=1
OEon=1
Ready
7
Wait
Not
Ready
Not
Ready
Sample Ready
Ready
Sample Data
Hold
SysClk
1
2
3
4
5
6
7
8
BusError
Error
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