參數(shù)資料
型號(hào): PPC403GC-JA33C1
元件分類: 32位微控制器
英文描述: 32-Bit Microprocessor
中文描述: 32位微處理器
文件頁數(shù): 36/48頁
文件大小: 768K
代理商: PPC403GC-JA33C1
IBM PowerPC 403GC
36
SRAM, ROM or I/O Burst Read with Wait and Hold
Bank Register Bit Settings
Notes:
1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword.
2. See Table 19 on page 32 for WBE signal definitions based on bus width.
3. See waveform and note 3 on page 33. WBE signals can be read/write byte enables based on the setting of a
control bit in the IOCR. See waveform and note 3 on page 33.
4. Wait must be programmed to a value
(CSon + OEon). If Wait > (CSon + OEon), then all signals will retain the
values shown in cycle 3 until the Wait timer expires.
5. If Hold is programmed > 001, all 403GC output signals retain the values shown in cycle 7 until the Hold timer
expires.
SLF
Burst
Mode
Bus
Width
Ready
Enable
Wait
States
Burst
Wait
CSon
OEon
WEon
WEoff
Hold
Bit 13
Bit 14
Bits
15:16
Bit 17
Bits
18:21
Bits
22:23
Bit 24
Bit 25
Bit 26
Bit 27
Bits
28:30
0 or 1
1
xx
0
0001
00
0 or 1
0 or 1
x
x
001
Valid BE
BE
BE
Valid BE
A6:29,
1
WBE2[A30],
WBE3[A31]
R/W
CSx
5
OE
4,5
WBE0:3
2,3
CSon=0
CSon=1
CSon=0
CSon=0,1
SysClk
1
2
3
4
5
6
7
8
Address1
Addr2
Addr3
Address4
D1
D2
D3
D4
Wait + 1 Cycles
5
Hold
Cycles
Cycles
Cycles
6
BusError
Error
Error
Error
Error
D0:31
BE0:3
3
BLast
4
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