參數(shù)資料
型號(hào)： PMS430E337
英文描述： 16-Bit Ultra-Low-Power Microcontroller. 32kB EPROM. 1KB RAM. USART. HW multiplier. 120 segment LCD
中文描述： 16位超低功耗微控制器。具有32kB存儲(chǔ)器。 1kB的內(nèi)存。的USART。硬件乘法器。 120段LCD
文件頁(yè)數(shù)： 15/29頁(yè)
文件大?。?/td> 411K
代理商： PMS430E337
MSP430x11x
MIXED SIGNAL MICROCONTROLLERS
SLAS196C
–
DECEMBER 1998
–
REVISED MARCH 2003
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
inputs Px.x, TAx
PARAMETER
TEST CONDITIONS
VCC
3 V/ 5 V
MIN
1.5
NOM
MAX
UNIT
cycle
P t P1 P2 P1
Port P1, P2: P1.x to P2.x,
External trigger signal for the interrupt flag (see Note 1)
External trigger signal for the interru t flag, (see Note 1)
t P2
t(int)
External Interrupt timing
3 V
540
ns
5 V
270
3 V/ 5 V
1.5
cycle
t(cap)
Timer_A, capture timing
TA0, TA1, TA2. (see Note 2)
3 V
540
ns
5 V
270
NOTES:
1. The external signal sets the interrupt flag every time the minimum tint cycle and time parameters are met. It may be set even with
trigger signals shorter than tint. Both the cycle and timing specifications must be met to ensure the flag is set.
2. The external capture signal triggers the capture event every time when the minimum tcap cycles and time parameters are met. A
capture may be triggered with capture signals even shorter than tcap. Both the cycle and timing specifications must be met to ensure
a correct capture of the 16-bit timer value and to ensure the flag is set.
internal signals TAx, SMCLK at Timer_A
PARAMETER
TEST CONDITIONS
VCC
3 V
MIN
dc
NOM
MAX
UNIT
f(IN)
Input frequency
Internal TA0 TA1 TA2 tH= tL
Internal TA0, TA1, TA2, tH = tL
10
MHz
5 V
dc
15
f(TAint)
Timer_A clock frequency
Internally, SMCLK signal applied
3 V/5 V
dc
fSystem
outputs P2x, TAx
PARAMETER
TEST CONDITIONS
VCC
3 V/5 V
MIN
NOM
MAX
1.1
UNIT
f(P20)
f(TAx)
Output frequency
P2.0/ACLK,
CL = 20 pF
CL = 20 pF
fP20 = 1.1 MHz
fP20 = fXTCLK
fP20 = fXTCLK/n
CL = 20 pF,
MHz
TA0, TA1, TA2,
3 V/5 V
dc
fSystem
60%
40%
t(Xdc)
P2.0/ACLK, CL = 20 pF
3 V/ 5 V
35%
65%
Duty cycle of O/P frequency
50%
t(TAdc)
TA0, TA1, TA2,
Duty cycle = 50%
3 V/ 5 V
0
±
50
ns
PUC/POR
PARAMETER
TEST CONDITIONS
MIN
NOM
150
MAX
250
UNIT
μ
s
t(POR_Delay)
TA =
–
40
°
C
TA = 25
°
C
TA = 85
°
C
1.5
2.4
V
VPOR
POR
VCC= 3 V/5 V
VCC = 3 V/5 V
1.2
2.1
V
0.9
1.8
V
V(min)
t(reset)
0
2
0.4
V
μ
s
PUC/POR
Reset is accepted internally
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