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RELEASED
DATA SHEET
PM7366 FREEDM-8
ISSUE 4
PMC-1970930
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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CONTENTS
1
FEATURES ....................................................................................................................... 1
2
APPLICATIONS ................................................................................................................ 3
3
REFERENCES.................................................................................................................. 4
4
APPLICATION EXAMPLES .............................................................................................. 5
5
BLOCK DIAGRAM ............................................................................................................ 6
6
DESCRIPTION.................................................................................................................. 7
7
PIN DIAGRAM................................................................................................................... 9
8
PIN DESCRIPTION..........................................................................................................11
9
FUNCTIONAL DESCRIPTION........................................................................................ 33
9.1
HIGH-LEVEL DATA LINK CONTROL PROTOCOL........................................... 33
9.2
RECEIVE CHANNEL ASSIGNER...................................................................... 34
9.2.1
LINE INTERFACE............................................................................. 34
9.2.2
PRIORITY ENCODER...................................................................... 34
9.2.3
CHANNEL ASSIGNER ..................................................................... 35
9.2.4
LOOPBACK CONTROLLER ............................................................ 35
9.3
RECEIVE HDLC PROCESSOR / PARTIAL PACKET BUFFER ........................ 35
9.3.1
HDLC PROCESSOR........................................................................ 36
9.3.2
PARTIAL PACKET BUFFER PROCESSOR..................................... 36
9.4
RECEIVE DMA CONTROLLER......................................................................... 38
9.4.1
DATA STRUCTURES ....................................................................... 38
9.4.2
DMA TRANSACTION CONTROLLER ............................................. 48
9.4.3
WRITE DATA PIPELINE/MUX.......................................................... 48
9.4.4
DESCRIPTOR INFORMATION CACHE........................................... 48