參數(shù)資料
型號(hào)： PM6641TR
廠(chǎng)商： STMICROELECTRONICS
元件分類(lèi)： 穩(wěn)壓器
英文描述： SWITCHING REGULATOR, 1100 kHz SWITCHING FREQ-MAX, QCC48
封裝： 7 X 7 MM, 1 MM HEIGHT, LEAD FREE, VQFP-48
文件頁(yè)數(shù)： 14/47頁(yè)
文件大?。?/td> 2254K
代理商： PM6641TR
PM6641
Device description
Doc ID 13510 Rev 3
21/47
the loop voltage reference is increased linearly from zero up to 0.8V in a long time (up to a
couple of milliseconds) (see Chapter 7.6: Outputs soft-start on page 28 for details).
When the EN_1S8 pin goes low, the VDDQ rail output capacitor is discharged through
internal discharge MOSFET and, at the end of the capacitor discharge, the low side power
MOSFET is eventually closed (see Chapter 7.7: Outputs soft-end on page 29 for details).
The Power Good signal (PG_1S8 pin) is an open drain output, shorting the output to GND in
the following conditions:
●
When the 1.8 V rail output voltage is outside +/- 10% range from nominal value
●
When a protection (UV, OV, thermal) has been triggered
●
When the regulator is in soft-start.
When VDDQ and VTT rails are enabled, PG_1S8 is left floating and, as a consequence,
pulled-up by the external pull-up resistor, if both the rails are inside +/- 10% range of nominal
value. The PG_1S8 pin can sink current up to 4 mA when it’s asserted low.
7.1.2
VTT LDO and VTTREF buffered reference
The PM6641 provides the required DDR2/3 reference voltage on VTTREF pin. The internal
buffer tracks half the voltage on VOUT_1S8 pin and has a sink and source capability up to
15 mA with an accuracy of ±2% referred to the VDDQ half.
Higher currents rapidly deteriorate the output accuracy. A 10 nF to 100 nF (33 nF typical)
bypass capacitor to SGND is required for stability.
The VTT low-drop-out linear regulator has been designed to sink and source up to 2 A peak
current and 1 A continuously. The VTT voltage tracks VTTREF within ±35 mV. A remote
voltage sensing pin (VTTFB) is provided to recovery voltage drops due to parasitic
resistance. In DDR2/3 applications, the linear regulator input LDOIN is typically connected
to VDDQ output; connecting LDOIN pin to a lower voltage (if available in the system)
reduces the power dissipation of the LDO, but a minimum drop-out voltage must be
guaranteed, depending on the maximum current expected.
A minimum output capacitance of 20 F (2x10 F or single 22 F ceramic capacitors) is
enough to assure stability and fast load transient response.
According to DDR2/3 JEDEC specifications, when the system enters the suspend-to-RAM
state (S5 high and S3 low) the LDO output is left in high-impedance while VTTREF and
VDDQ are still alive. When the suspend-to-disk state (S3 and S5 tied to ground) is entered,
all outputs are actively discharged by a tracking or a non-tracking discharge as selected
through the DSCG pin (see Chapter 7.7: Outputs soft-end on page 29 for details).
7.1.3
VTT and VTTREF soft-start
Soft-start on VTT and VTTREF outputs is achieved by current clamping. The LDO linear
regulator is provided of a current fold-back protection: when the output voltage exits the
internal ±10% VTT-Good window, the output current is clamped at ±1 A. Re-entering VTT-
Good window releases the current limit clamping. The fold-back mechanism naturally
implements a two steps soft-start charging the output capacitors with a 1 A constant current.
Something similar occurs at VTTREF pin, where the output capacitor is smoothly charged at
a fixed 40 mA (typ) current limit.
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