參數(shù)資料
型號(hào)： PM5945
廠商： PMC-SIERRA INC
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： CONN
中文描述： ATM NETWORK INTERFACE, XFO
文件頁(yè)數(shù)： 7/84頁(yè)
文件大?。?/td> 1666K
代理商： PM5945
S
TANDARD
P
RODUCT
PMC-Sierra, Inc.
PM5945 -UTP5
PMC-940202 ISSUE 2. APRIL 7, 1995
______________________________________________________________________________________________
APP_SAPI_UTP5
______________________________________________________________________________________________
3
sinks cells provided by the buffer interface and sources cells to the buffer interface.
Below, the S/UNI is briefly described.
The S/UNI receives SONET/SDH frames via a bit serial interface, and processes
section, line, and path overhead. It performs framing (A1, A2), descrambling, detects
alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2,
B3), accumulating error counts at each level for performance monitoring purposes.
Line and path far end block error indications (FEBE) are also accumulated. The
S/UNI interprets the received payload pointers (H1, H2) and extracts the
synchronous payload envelope which carries the received ATM cell payload.
The S/UNI frames to the ATM payload using cell delineation. Header check
sequence (HCS) error correction is provided. Idle/unassigned cells may be
dropped according to a programmable filter. Cells are also dropped upon detection
of an uncorrectable HCS error. The ATM cell payloads are descrambled. The ATM
cells that are passed are written to a four cell FIFO buffer. The received cells are
read from the FIFO using a generic 8-bit wide datapath interface. Counts of received
ATM cell headers that are erred and uncorrectable, and also those that are erred
and correctable, are accumulated independently for performance monitoring
purposes.
The S/UNI transmits SONET/SDH frames via a bit serial interface, and formats
section, line, and path overhead bytes appropriately. It performs framing pattern
insertion (A1, A2), scrambling, alarm signal insertion, and inserts section, line, and
path bit interleaved parity (B1, B2, B3) as required to allow performance monitoring
at the far end. Line and path far end block error indications (FEBE) are also
inserted. The S/UNI generates the payload pointer (H1, H2) and inserts the
synchronous payload envelope which carries the ATM cell payload. The S/UNI also
supports the insertion of a large variety of errors into the transmit stream, such as
framing pattern errors, bit interleaved parity errors, and illegal pointers, which are
useful for system diagnostics and tester applications.
Transmit ATM cells are written to an internal four cell FIFO using a generic 8-bit wide
datapath interface. Idle/unassigned cells are automatically inserted when the
internal FIFO contains less than one cell. The S/UNI provides generation of the
header check sequence and scrambles the payload of the ATM cells. Each of these
transmit ATM cell processing functions can be enabled or bypassed.
The S/UNI is configured, controlled and monitored via the microprocessor interface
on the UTOPIA connector.
For a complete description of the S/UNI, please refer to PMC-Sierra's PM5345
datasheet.
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