參數(shù)資料
型號： PM5945
廠商： PMC-SIERRA INC
元件分類： 數(shù)字傳輸電路
英文描述： CONN
中文描述： ATM NETWORK INTERFACE, XFO
文件頁數(shù)： 14/84頁
文件大?。?/td> 1666K
代理商： PM5945
S
TANDARD
P
RODUCT
PMC-Sierra, Inc.
PM5945 -UTP5
PMC-940202 ISSUE 2. APRIL 7, 1995
______________________________________________________________________________________________
APP_SAPI_UTP5
______________________________________________________________________________________________
10
Software Reset
The software reset bit is at binary address 1110xxxxx (the most significant bit is at
the far left and the least significant is at the far right). The least significant 5 bits of
the address are don't cares. Writing a binary xxxxxxx1 to this address will hold the
S/UNI, the FIFO, and the PALs reset. Writing a binary xxxxxxx0 to this address will
remove the reset. The most significant 7 bits of data are don't cares. This is a write-
only bit. A hardware reset removes the software reset.
Transmit Loopback Enable
The transmit loopback enable bit is at binary address 1111xxxxx (the most
significant bit is at the far left and the least significant is at the far right). The least
significant 5 bits of the address are don't cares. Writing a binary xxxxxxx1 to this
address will mux the transmit output data going to the optics, into the inputs of the
clock and data recovery PLL. This is all done inside the Cypress CY7B951 device.
This allows a diagnostic loopback to be done at the Cypress part to verify the
connections and functionality between the Cypress device and the S/UNI device.
Writing a binary xxxxxxx0 to this address will disable transmit diagnostic loopback.
The most significant 7 bits of data are don't cares. This is a write only bit. A
hardware reset removes the transmit loopback enable (if it was set).
INTERFACE DESCRIPTION
UTOPIA Interface
The UTOPIA Interface makes the S/UNI drop side receive and transmit signals
compatible with the UTOPIA 1.04 interface specification. It consists of two high
speed 22V10 PALs, two high speed IDT74FCT377C buffers, and a receive
IDT72201 clocked FIFO. The 22V10 PALs can be replaced with faster versions if
you must run at a higher than 20 MHz TxClk and RxClk clock signals.
The Transmit drop side interface is controlled by the ATM layer through the edge
connector. All the transmit signals from the ATM layer change with respect to the
TxClk. All the input signals to the ATM layer are sampled on the rising edge of the
TxClk.
The S/UNI device asserts the TCA signal when it has a complete empty cell
available. This signal goes to the PAL (U17) and causes the TxFullB signal to the
ATM layer to be de-asserted (high). The ATM layer asserts the TxClavB signal (low)
when it has a complete Cell of data to transfer to the PHY device. The TxEnbB
signal from the ATM layer (Vicksburg card) is the output of the TxFullB signal from
the PHY layer gated with the TxClavB signal from the ATM layer. The way the
TxEnbB signal goes active (low) depends on whether the ATM layer is ready to send
a cell of data before the PHY layer becomes available to accept the data, or whether
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