
PM5352
PMC-Sierra,Inc.
155 Mbit/s ATM and Packet-Over-SONET/SDH Physical Layer Device
S/UNI
-155-STAR
PMC-991722 (r1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS
’
INTERNAL USE
Copyright PMC-Sierra, Inc. 2000
FEATURES
Single channel ATM and Packet-over-
SONET OC-3c (155 Mbit/s) PHY.
Provides on-chip clock and data
recovery and clock synthesis.
Exceeds Bellcore-GR-253 jitter
requirements.
Inserts and extracts ATM cells or POS
packets into/from SONET SPE.
Filters and captures Automatic
Protection Switch byes (K1 and K2)
and detects APS byte failure.
Detects signal degrade and signal
failure thresholds crossing alarms.
Captures and debounces
synchronization status byte (S1).
Extracts and inserts the 16 or 64-byte
section trace (J0) and path trace (J1)
messages.
Extracts and inserts section/line data
communication channels (DCC).
Provides circuitry to meet holdover,
wander and long term stability.
Provides a generic 8-bit
microprocessor interface for device
control and register access.
Provides standard IEEE 1149.1 JTAG
test port for boundary scan.
ATM
Implements the ATM Forum User
Network Interface Specification.
Performs cell payload scrambling and
descrambling.
Provides a UTOPIA Level 2-compliant
system interface.
Provides synchronous cell transmit
and receive FIFO buffers.
PACKET-OVER-SONET
Generic design that supports packet-
based protocols like PPP, HDLC and
Frame Relay.
Implements the PPP over SONET/
SDH specification according to RFC
2615 and 1662 of the IETF.
Performs flag sequence detection and
insertion.
Performs CRC-CCITT and CRC-32
FCS generation and validation.
Performs byte stuffing and destuffing.
Checks for minimum and maximum
packet lengths.
Provides a SATURN-compatible
Packet-over-SONET POS-PHY Level
2 Interface.
PACKAGING
Low power, 3.3 V CMOS technology.
Packaged in a 304-pin Ball Grid Array
(BGA) package.
Industrial temperature range (-40° to
+85°C).
APPLICATIONS
DSLAM uplinks.
Access concentrators.
Layer 3 switches.
ATM switches.
BLOCK DIAGRAM
Path Trace
Buffer
CP
CN
Line
DCC
Insert
SD
REFCLK
RXD+
RXD-
ATB[3:0]
TXD+
TXD-
TXC+
TXC-
TDAT[15:0]
TERR
TEOP
TPRTY
TSOC/TSOP
TCA
TADR
TMOD
TENB
TFCLK
DTCA/DTPA
RSOC/RSOP
RPRTY
RADR
RCA/RVAL
RFCLK
RDAT[15:0]
DRCA/DRP
REOP
RERR
RMOD
PHY_OEN
RENB
Receive
Path O/H
Processor
Receive
Section O/H
Processor
Receive
Line O/H
Processor
Receive
POS Frame
Processor
Receive
ATM Cell
Processor
Section Trace
Buffer
W
S
Transmit
Line
Interface
Receive
Line
Interface
D
I
A
R
A
C
W
R
Microprocessor
Interface
T
T
T
T
T
JTAG
Test Access
Port
T
T
T
T
Section
DCC
Insert
T
T
T
Transmit
Path O/H
Processor
Transmit
Section O/H
Processor
Transmit
Line O/H
Processor
Transmit
ATM Cell
Processor
Transmit
POS Frame
Processor
UTOPIA
Level 2 /
POS-PHY
Level 2
System
Interface
Line
DCC
Extract
R
R
Section
DCC
Extract
R
R
R
R
R
Receive
APS, Sync,
BERM