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參數(shù)資料
| 型號： | PM5316-BI |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH Payload Extractor/Aligner(4 x 155 Mbit/s) |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA520 |
| 封裝： | 40 X 40 MM, 1.54 MM HEIGHT, 1.27 MM PITCH, SBGA-520 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大?。?/td> | 53K |
| 代理商： | PM5316-BI |
PM5316
PMC-Sierra,Inc.
Quad Channel 155 Mbit/s SONET/SDH Framer and Aligner
SPECTRA-4x155
PMC-2000327 (R2)
PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC., AND FOR ITS CUSTOMERS
’
INTERNAL USE
Copyright PMC
-
Sierra, Inc. 2001
FEATURES
Monolithic four channel SONET/SDH
Payload Extractor/Aligner for use in
STS-3 (STM-1/AU-3) or STS-3c (STM-
1/AU-4) interface applications,
operating at serial interface speeds of
155.52 Mbit/s.
Provides integrated clock recovery and
clock synthesis to allow direct interface
to optical modules.
Each channel provides termination for
SONET Section and Line, SDH
Regenerator Section and Multiplexer
Section transport overhead, and path
overhead of three STS-1 (STM-0/AU-
3) paths or a single STS-3c (STM-
1/AU-4) path.
Each channel maps three STS-1
(STM-0/AU-3) payloads or a single
STS-3c (STM-1/AU-4) payload to
system timing reference,
accommodating plesiosynchronous
timing offsets between the references
through pointer processing.
The entire SONET/SDH transport and
path overheads are extracted to and
inserted from dedicated pins.
Frames to the SONET/SDH receive
stream and inserts framing bytes and
STS identification into the transmit
stream and processes or inserts the
transport overhead.
Interprets or generates the STS (AU)
pointer bytes (H1, H2, H3), extracts or
inserts the synchronous payload
envelope(s) and processes or inserts
the path overhead.
Supports Automatic Protection
Switching (APS):
Ring control port communication of
path REI and path RDI alarms;
Filters the APS channel (K1,K2)
bytes into internal registers; inserts
the APS channel into the transmit
stream.
Provides Time Slot Interchange (TSI)
function at the ADD and DROP
TelecomBus Interfaces for grooming
twelve STS-1 (STM-0/AU-3) paths.
Supports line loopback from the line
side receive stream to the transmit
stream and diagnostic loopback from
an ADD TelecomBus interface to a
DROP TelecomBus interface.
Provides a standard five signal
P1149.1 JTAG test port for boundary
scan board test purposes.
Provides a generic 8-bit
microprocessor bus interface for
configuration, control, and status
monitoring.
Low power 3.3 V CMOS with TTL
compatible digital inputs and
CMOS/TTL digital outputs.
Industrial temperature range (-40
°
C to
+85
°
C).
520 pin Super BGA package.
Supports clock recovery bypass for
use in applications where external
clock recovery is desired.
Complies with Bellcore GR-253-CORE
jitter tolerance, jitter transfer, and
intrinsic jitter criteria.
8-bit x 77.76 Mbit/s
TelecomBus
OR
4 x 8-bit x 19.44
Mbit/s TelecomBus
Receive
Path
Overhead
Tx Timeslot
Interchange
Tx
TelecomBus
System
Interface
8-bit x 77.76 Mbit/s
TelecomBus
OR
4 x 8-bit x 19.44
Mbit/s TelecomBus
Clock
Synthesis
Path Processing Slice x 12
Rx Timeslot
Interchange
TeleRx
System
Interface
Tx Pointer
Interpreter
(STS/
Tx
Telecom
Aligner
Add Bus
PRBS
Monitor
Tx Path
O/H
Processor
Transmit Path Processing Slice
Transmit
Transport
O/H
4 x Serial
155.52 Mbit/s
Tx Path O/H
Controller
Control and
Status
Information
Path
Trace
Buffer
Rx
Aligner
Drop Bus
PRBS
Monitor
Rx Path
PrO/H
Receive Path Processing Slice
PMON
Rx Path O/H
Controller
Transmit
Path
Overhead
Control
and Status
Information
Receive O/H
Clock, Frame
Pulse, Receive
Transport
Overhead
JTAG Test
Access Port
Test Data
8-bit
Microprocessor
Bus
Microprocessor Interface
DPAIS and
TPAIS
Path AIS
Signals
Tx Line
Interface
Tx Section
OH
Processor
Tx Re-
Mulitplexer
Tx Ring
Control
Port
Tx Transport
Overhead
Controller
Tx Line OH
Processor
Channel Line
Side Top x 4
Rx Line
Interface
Clock and
Data
Recovery
Rx APS Syn-
Extractor and
Bit Error
Monitor
Section
Trace Buffer
Rx Section
OH
Processor
Rx Transport
Overhead
Controller
WAN Syn-
chronization
Controller
Rx Line OH
Processor
Rx Ring
Control
Port
4 x Serial
155.52 Mbit/s
Rx De-
Mulitplexer
BLOCK DIAGRAM
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PM5316BIP | 制造商:PMC-Sierra 功能描述: |
| PM5317 | 制造商:PMC 制造商全稱:PMC 功能描述:SONET/SDH Payload Extractor/Aligner for 9953 Mbit/s |
| PM5317-FI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| PM5319 | 制造商:PMC 制造商全稱:PMC 功能描述:SONET/SDH Interface for 622 & 155 Mbit/s |
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