參數(shù)資料
型號(hào): PM5317
廠商: PMC-Sierra, Inc.
英文描述: SONET/SDH Payload Extractor/Aligner for 9953 Mbit/s
中文描述: SONET / SDH的凈荷提取/光刻機(jī)的9953兆位/秒
文件頁(yè)數(shù): 1/2頁(yè)
文件大?。?/td> 82K
代理商: PM5317
PM5317
Preliminary
SONET/SDH Payload Extractor/Aligner for 9953 Mbit/s
SPECTRA-9953
PMC-2000992 (P2)
PROPRIETARY AND CONFIDENTIAL TO PMC
-
SIERRA, INC., AND FOR ITS CUSTOMERS
INTERNAL USE
Copyright PMC
-
Sierra, Inc. 2001
FEATURES
Monolithic single channel STS-
192/STM-64 or quad channel STS-
48/STM-16 SONET/SDH Payload
extractor/aligner.
Designed for use in interface
applications operating at serial
interface speeds of up to OC-192
rates:
single STS-192c (STM-64/
AU4-64c);
single STS-192 (STM-64/AU4-
16c/AU4-4c/AU4/AU3) channelized
to STS-1;
quad STS-48c (STM-16/AU4-16c);
quad STS-48 (STM-16/
AU4-4c/AU4/AU3);
pointer processing for STS-1,
STS-3c, STS-12c, STS-24c, STS-
48c, and STS-192c traffic.
In single STS-192/STM-64 mode,
supports a duplex 16-bit 622 MHz
LVDS line side interface for direct
connection to external clock recovery,
clock synthesis and serializer-
deserializer components.
In quad STS-48/STM-16 mode,
supports four duplex 4-bit 622 MHz
LVDS line side interfaces for direct
connection to external clock recovery,
clock synthesis and serializer-
deserializer components.
Standard OIF SFI-4 (16 x 622 Mbit/s)
line side interface.
Each channel provides termination for
SONET Section, Line and Path
overhead or SDH Regenerator
Section, Multiplexer Section and High
Order Path overhead.
Provides a 16-bit 622 Mbit/s 8B10B
encoded (777.7 MHz) ADD and DROP
serial TelecomBus interface for
grooming a single STS-192/STM-64
stream.
Provides four 4-bit 622 Mbit/s 8B10B
encoded (777.7 MHz) ADD and DROP
serial TelecomBus interfaces for
grooming four STS-48/STM-16
streams.
Maps SONET/SDH payloads to
system timing, accommodating
plesiochronous timing offsets between
the line and system timing references,
through pointer processing.
Provides STS-12 cross-connect
capability for grooming traffic at the
ADD and DROP TelecomBus
interface.
The entire SONET/SDH transport
overhead is extracted to and inserted
from dedicated pins. Path BIP-8 error
counts are extracted to dedicated pins.
Frames to the SONET/SDH receive
stream, inserts framing bytes and STS
identification into the transmit stream,
and processes or inserts the transport
overhead.
Interprets or generates the STS (AU)
pointer bytes (H1, H2, H3), extracts or
inserts the synchronous payload
envelope(s) and processes or inserts
the path overhead.
Rx Ring
Control
Port
OC-192 Mode:
16 x 622 MHz
LVDS
4 x OC-48 Mode:
4 x 4 x 622 MHz
LVDS
OC-192 Mode:
16 x 777 MHz LVDS
4 x OC-48 Mode:
4 x 4 x 777 MHz
LVDS
OC-192 Mode:
16 x 622 MHz
LVDS
4 x OC-48 Mode:
4 x 4 x 622 MHz
LVDS
OC-192 Mode:
16 x 777 MHz LVDS
4 x OC-48 Mode:
4 x 4 x 777 MHz
LVDS
Status
Information
Tx Pointer
Interpreter
Tx
Telecom
Aligner
Path
Trace
Processor
Tx Path O/H
Processor
16-bit
Microprocessor
Bus
Microprocessor Interface
Quad 2488
or 9953
Mode
Test Data
JTAG Test
Access Port
Tx Line
Interface
Transmit
Transport
O/H
Section
Trace
Processor
Tx Transport
O/H Processor
Control
and
Status
Information
Path Processing Slice:
192 x STS-1
Path
Trace
Processor
Rx Path O/H
Processor
STS-12
XC
8B/10B
Encoder
B3E
Rx Line
Interface
Rx
Telecom
Aligner
Receive O/H Clock, Frame
Pulse
Receive Transport Overhead
Receive Section/Line DCC and
Clock
Alarm
Reporting
SONET/SDH
Alarm
Reporting
Controller
Rx APS
Sync
Extractor
&
Bit Error
Monitor
Section
Trace
Processor
RX Transport
O/H Processor
Tx Ring
Control Port
PISO
LVDS
Transmitter
STS-12
XC
8B/10B
Decoder
DRU
LVDS
Receiver
Transport
Processing Slice x 4
BLOCK DIAGRAM
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