參數(shù)資料
型號(hào)： PLV16V8
廠商： Lattice Semiconductor Corporation
英文描述： Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic
中文描述： 低電壓，零功率20引腳電子工程的CMOS通用可編程陣列邏輯
文件頁(yè)數(shù)： 2/22頁(yè)
文件大?。?/td> 425K
代理商： PLV16V8
2
PALLV16V8-10 and PALLV16V8Z-20 Families
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
The PALLV16V8 is a low-voltage, EE CMOS version of the PALCE16V8.
The PALLV16V8Z is a low-voltage, EE CMOS version of the PALCE16V8. In addition, the
PALLV16V8Z has zero standby power and an unused product term disable feature for reduced
power consumption.
The PALLV16V8 is a universal PAL device. It has eight independently configurable macrocells
(MC
0
-MC
7
). Each macrocell can be configured as registered output, combinatorial output,
combinatorial I/O or dedicated input. The programming matrix implements a programmable AND
logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary
outputs to provide user-programmable input signal polarity. Pins 1 and 11 serve either as array
inputs or as clock (CLK) and output enable (OE), respectively, for all flip-flops.
Unused input pins should be tied directly to V
unprogrammed (disconnected) assume the logical HIGH state and product terms with both true
and complement of any input signal connected assume a logical LOW state.
CC
or GND. Product terms with all bits
The programmable functions on the PALLV16V8 are automatically configured from the user’s
design specification. The design specification is processed by development software to verify the
design and create a programming file. This file, once downloaded to a programmer, configures the
device according to the user’s desired function.
Programmable AND Array
32 x 64
MACRO
MC0
MACRO
MC1
MACRO
MC2
MACRO
MC3
MACRO
MC4
MACRO
MC5
MACRO
MC6
MACRO
MC7
OE
/I
9
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
8
I
1
- I
8
CLK/
I0
17713D-1
I/O
5
I/O
6
I/O
7
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