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參數(shù)資料
| 型號： | PLUS173BA |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | Programmable logic arrays 22 】 42 】 10 |
| 中文描述： | OT PLD, 15 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 73K |
| 代理商： | PLUS173BA |
Philips Semiconductors Programmable Logic Devices
Product specification
PLUS173B/D
Programmable logic arrays
(22
×
42
×
10)
October 22, 1993
38
LOGIC PROGRAMMING
The PLUS173 series is fully supported by
industry standard (JEDEC compatible) PLD
CAD tools, including Philips Semiconductors
SNAP design software package. ABEL
and
CUPL
design software packages also
support the PLUS173 architecture.
All packages allow Boolean and state
equation entry formats. SNAP, ABEL and
CUPL also accept, as input, schematic
capture format.
PLUS173 logic designs can also be
generated using the program table entry
format, which is detailed on the following
page. This program table entry format is
supported by SNAP only.
To implement the desired logic functions, the
state of each logic variable from logic
equations (I, B, O, P, etc.) is assigned a
symbol. The symbols for TRUE,
COMPLEMENT, INACTIVE, PRESET, etc.,
are defined below.
PROGRAMMING AND
SOFTWARE SUPPORT
Refer to Section 9
(Development Software)
and Section 10
(Third-Party Programmer/
Software Support)
of this data handbook for
additional information.
AND ARRAY – (I, B)
CODE
O
STATE
INACTIVE
1, 2
CODE
H
STATE
CODE
STATE
I, B
CODE
STATE
I, B
L
–
P, D
I, B
I, B
I, B
P, D
I, B
I, B
I, B
P, D
I, B
I, B
I, B
P, D
I, B
I, B
I, B
DON’T CARE
OR ARRAY – (B)
VIRGIN STATE
A factory shipped virgin device contains all
fusible links intact, such that:
1. All outputs are at “H” polarity.
2. All P
n
terms are disabled.
3. All P
n
terms are active on all outputs.
NOTES:
1. This is the initial unprogrammed state of all link pairs. It is normally associated with all unused
(inactive) AND gates P
n
, D
n
.
2. Any gate P
n
, D
n
will be unconditionally inhibited if both the true and complement of any input
(I, B) are left intact.
ABEL is a trademark of Data I/O Corp.
CUPL is a trademark of Logical Devices, Inc.
CODE
ACTIVE LEVEL
LOW
(INVERTING)
L
CODE
ACTIVE LEVEL
HIGH
1
(NON-INVERTING)
H
S
X
B
S
X
B
OUTPUT POLARITY – (B)
CODE
INACTIVE
A
CODE
P
n
STATUS
ACTIVE
1
P
S
P
n
STATUS
P
S
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PLUS173BN | Programmable logic arrays 22 】 42 】 10 |
| PLUS173D | Programmable logic arrays 22 】 42 】 10 |
| PLUS405AA | Fuse-Programmable PLD |
| PLUS405AN | Fuse-Programmable PLD |
| PLV16V8 | Low Voltage, Zero Power 20-Pin EE CMOS Universal Programmable Array Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLUS173BN | 制造商:NXP Semiconductors 功能描述: |
| PLUS173D | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Programmable logic arrays 22 】 42 】 10 |
| PLUS173DA | 制造商:Siemens 功能描述: |
| PLUS173DN | 制造商:Philips 功能描述:Programmable Logic Arrays 24-Pin PDIP |
| PLUS20L8-7A | 制造商:NXP Semiconductors 功能描述: |
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