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參數(shù)資料
| 型號： | PLRXXL-SC-S43-C1 |
| 廠商： | JDS UNIPHASE CORP |
| 元件分類： | 光收發(fā) |
| 英文描述： | FIBER OPTIC TRANSCEIVER, 840-860nm, 10312.5Mbps(Tx), 10312.5Mbps(Rx), PANEL MOUNT, LC CONNECTOR |
| 封裝： | ROHS COMPLIANT PACKAGE-30 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 573K |
| 代理商： | PLRXXL-SC-S43-C1 |
4
ROHS COMPLIANT XFP OPTICAL TRANSCEIVER – 850NM
FOR UP TO 300M REACH
Low Speed Signaling
Low speed signaling is based on low voltage TTL (LVTTL) operating at a nominal
voltage of 3.3 V.
SCL/SDA: Two wire Serial interface clock and data line. Hosts should use a pull-up
resistor connected to Vcc 3.3 V on the two-wire interface SCL (clock), SDA (data),
and all low speed outputs.
Mod_NR: Output pin. When asserted high indicates that the module has detected
a condition that renders Tx and or Rx data invalid.
Mod_DeSel: Input pin. When held low by the host the module responds to 2-wire
serial communication commands. When high the module does not respond to or
acknowledge any 2-wire interface communication from the host.
Interrupt: Output pin. When low indicates possible module operational fault or a
status critical to the host system.
TX_DIS: Input pin. When asserted high the transmitter output is turned off.
Mod_ABS: Output pin. Asserted high when the XFP module is absent and is pulled
low when the XFP module is inserted.
RX_LOS: Output pin. Asserted high when insufcient optical power for reliable
signal reception is received.
P_Down/RST: Multifunction input pin. The module uses less than 1.5W and
therefore is always compliant to the power down specication. The module is fully
functional when P_Down is asserted high. Reset can be initiated by pulling this pin
high and then low. The reset pulse is generated on the falling edge of the P-Down
signal. Following reset, the internal PLL’s must reacquire lock and will temporarily
indicate a Mod_NR failure until the PLL’s reacquire lock.
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