參數(shù)資料
型號(hào)： PLRXPL-VI-S24-22
廠商： JDS UNIPHASE CORP
元件分類： 光收發(fā)
英文描述： FIBER OPTIC TRANSCEIVER, 830-860nm, 2125Mbps(Tx), 2125Mbps(Rx), LC CONNECTOR
封裝： ROHS COMPLIANT, 20 PIN
文件頁(yè)數(shù)： 20/22頁(yè)
文件大?。?/td> 724K
代理商： PLRXPL-VI-S24-22
7
ROHS-COMPLIANT 2.125, 1.25 AND 1.063 GBPS 850 NM TRANSCEIVER
Pin Number
Symbol
Name
Description
Receiver
8
LOS
Loss of Signal Out (OC)
Sufcient optical signal for potential BER < 1x10-12 = Logic “0”
Insufcient optical signal for potential BER < 1x10-12 = Logic “1”
This pin is open collector compatible, and should be pulled
up to Host Vcc with a 10 k resistor.
9, 10, 11, 14
VeeR
Receiver Signal Ground
These pins should be connected to signal ground on the host board.
12
RD-
Receiver Negative DATA
Light on = Logic “0” Output
Out (PECL)
Receiver DATA output is internally AC coupled and series
terminated with a 50 resistor.
13
RD+
Receiver Positive DATA
Light on = Logic “1” Output
Out (PECL)
Receiver DATA output is internally AC coupled and series
terminated with a 50 resistor.
15
VccR
Receiver Power Supply
This pin should be connected to a ltered +3.3V power supply
on the host board. See Application schematics on page 5 for
ltering suggestions.
7
Rate Select
Rate Select (LVTTL)
This pin has an internal 30K pulldown to ground. An input
signal will not affect module performance
Transmitter
3
TX Disable
Transmitter Disable In (LVTTL)
Logic “1” Input (or no connection) = Laser off
Logic “0” Input = Laser on
This pin is internally pulled up to Vcc
T with a 10 k resistor.
1, 17, 20
VeeT
Transmitter Signal Ground
These pins should be connected to signal ground on the host board.
2
TX Fault
Transmitter Fault Out (OC)
Logic “1” Output = Laser Fault (Laser off before t_fault)
Logic “0” Output = Normal Operation
This pin is open collector compatible, and should be pulled
up to Host Vcc with a 10 k resistor.
16
VccT
Transmitter Power Supply
This pin should be connected to a ltered +3.3V power supply
on the host board.
See Application schematics on page 5 for ltering suggestions.
18
TD+
Transmitter Positive DATA In
Logic “1” Input = Light on
(PECL)
Transmitter DATA inputs are internally AC coupled and
terminated with a differential 100 resistor.
19
TD-
Transmitter Negative DATA In
Logic “0” Input = Light on
(PECL)
Transmitter DATA inputs are internally AC coupled and
terminated with a differential 100 resistor.
Module Denition
4, 5, 6
MOD_DEF(0:2)
Module Denition Identiers
Serial ID with SFF 8472 Diagnostics (See section 3.1)
Module Denition pins should be pulled up to Host Vcc with
10 k resistors.
Table 1 Transceiver pin descriptions
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