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參數(shù)資料
| 型號(hào)： | PLRXPL-VI-S24-22 |
| 廠商： | JDS UNIPHASE CORP |
| 元件分類： | 光收發(fā) |
| 英文描述： | FIBER OPTIC TRANSCEIVER, 830-860nm, 2125Mbps(Tx), 2125Mbps(Rx), LC CONNECTOR |
| 封裝： | ROHS COMPLIANT, 20 PIN |
| 文件頁數(shù)： | 18/22頁 |
| 文件大小： | 724K |
| 代理商： | PLRXPL-VI-S24-22 |
5
ROHS-COMPLIANT 2.125, 1.25 AND 1.063 GBPS 850 NM TRANSCEIVER
Recommended connections to the PLRXPL-VI-S24-22 transceiver are shown in
gure 2 below.
Section 2
Application Schematics
Notes
Power supply ltering components should be placed as close to the V
cc pins of the host connector as possible for optimal performance.
PECL driver and receiver will require biasing networks. Please consult application notes from suppliers of these components. CML I/O on the PHY are supported.
MOD_DEF(2) and MOD_DEF(1) should be bi-directional open collector connections in order to implement serial ID (MOD_DEF[0,1,2]) PLRXPL-VI-S24-22 transceiver.
R1 and R2 may be included in the output of the PHY. Check application notes of the IC in use.
* Transmission lines should be 100 differential traces. It is recommended that the termination resistor for the PECL Receiver (R3 + R4) be placed beyond the input pins of the
PECL Receiver. Series Source Termination Resistors on the PECL Driver (R1+R2) should be placed as close to the driver output pins as possible
Figure 2
Recommended application schematic for the PLRXPL-VI-S24-22 transceiver
Receiver (Tx Fault)
Vcc
10 k
?
Open Collector Driver
(Tx Disable)
Open Collector
Bidirectional
(Mod_Def(2))
Vcc
10 k
Ω
Vcc
Open Collector
Bidirectional
(Mod_Def(1))
10 k
Ω
Receiver
(Mod_Def(0))
10 k
Ω
Vcc
1 VeeT
2 Tx Fault
3 Tx Disable
4 MOD_DEF(2)
5 MOD_DEF(1)
6 MOD_DEF(0)
7 Rate Select
8 LOS
9 VeeR
10 VeeR
VeeT 20
TD- 19
TD+ 18
VeeT 17
VccT 16
VccR 15
VeeR
14
RD+ 13
RD- 12
VeeR
11
Rate Select
10 k
Ω
Vcc
Receiver (LOS)
R1* 50
Ω
R2* 50
Ω
Vcc +3.3V Input
L1
1
μH
L2
1
μH
Z* = 100
Ω
Z* = 100
Ω
R3*
50
Ω
R4*
50
Ω
PECL Driver
(TX DATA)
PECL Receiver
(RX DATA)
C1
10
μF
C2
0.1
μF
C5
10
μF
C4
0.1
μF
C3
0.1
μF
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