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參數(shù)資料
| 型號： | PLRXPL-VE-SG4-38 |
| 廠商： | JDS UNIPHASE CORP |
| 元件分類： | 光收發(fā) |
| 英文描述： | FIBER OPTIC TRANSCEIVER, 840-860nm, 2125Mbps(Tx), 2125Mbps(Rx), LC CONNECTOR |
| 封裝： | ROHS COMPLIANT PACKAGE |
| 文件頁數(shù)： | 17/22頁 |
| 文件大小： | 480K |
| 代理商： | PLRXPL-VE-SG4-38 |
4
ROHS-COMPLIANT 4.25 GBPS 850 NM ESFP TRANSCEIVERS;
EXTENDED/INDUSTRIAL TEMPERATURE & VOLTAGE
An open collector compatible Loss of Signal is provided. The LOS must be pulled
high on the host board for proper operation. A logic “0” indicates that light has
been detected at the input to the receiver (see Section 2.5 Optical characteristic,
Loss of Signal Assert/Deassert Time on page 9). A logic “1” output indicates that
insufcient light has been detected for proper operation.
Power supply ltering is recommended for both the transmitter and receiver. Fil-
tering should be placed on the host assembly as close to the Vcc pins as possible
for optimal performance.
Recommended “Application Schematics” are shown in Figure 2 on page 5.
Figure 1
Block diagram
Vcc_R
ROSA
R_Gnd
Vcc_R
RD-
RECEIVER
RD+
LOS
50
Vcc_T
TD+
Laser Driver
TD-
T_Gnd T_Fault
50
50
R_Gnd
16 Transmitter Power Supply
19 Transmitter
Negative Data In
18 Transmitter
Positive Data In
2 Transmitter Fault Out
1, 17, 20 Transmitter
Signal Ground
15 Receiver Power Supply
9, 10, 11, 14 Receiver
Signal Ground
8 Loss of Signal Out
13 Receiver Positive
Data Out
12 Receiver Negative
Data Out
6 MOD_DEF(0)
10K
3 Transmitter Disable In
TDis
7 Rate Select
5 MOD_DEF(1) Serial ID Clock
4 MOD_DEF(2) Serial ID Data
SCL
SDA
TOSA
Vcc_T
Management
Processor
EEPROM
30 k
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