- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368046 > PLL1706DBQRG4 3.3-V DUAL PLL MULTICLOCK GENERATOR PDF資料下載
參數(shù)資料
| 型號(hào)： | PLL1706DBQRG4 |
| 英文描述： | 3.3-V DUAL PLL MULTICLOCK GENERATOR |
| 中文描述： | 3.3 - V雙鎖相環(huán)MULTICLOCK發(fā)生器 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 187K |
| 代理商： | PLL1706DBQRG4 |
PLL1705
PLL1706
SLES046A
–
AUGUST 2002
–
REVISED SEPTEMBER 2002
www.ti.com
9
The master clock can be either a crystal oscillator placed between XT1 (pin 10) and XT2 (pin 11), or an external input to
XT1. If an external master clock is used, XT2 must be open. Figure 8 illustrates possible system clock connection options,
and Figure 9 illustrates the 27-MHz master clock timing requirement.
Crystal
PLL1705/PLL1706
Crystal
OSC
Circuit
27-MHz
Internal
Master
Clock
XT1
XT2
C2
C1
MCKO1
MCKO2
C1, C2 = 10 pF to 33 pF
Crystal Resonator Connection
PLL1705/PLL1706
XT1
XT2
MCKO1
MCKO2
External Clock Input Connection
External
Clock
Crystal
OSC
Circuit
27-MHz
Internal
Master
Clock
Figure 8. Master Clock Generator Connection Diagram
t(XT1H)
XT1
t(XT1L)
0.7 VCC
0.3 VCC
DESCRIPTION
SYMBOL
t
XT1H
t
XT1L
MIN
10
10
MAX
UNIT
ns
ns
Master clock pulse duration HIGH
Master clock pulse duration LOW
Figure 9. External Master Clock Timing Requirement
The PLL1705/6 provides a very low-jitter, high-accuracy clock. SCKO0 outputs a fixed 33.8688-MHz clock, SCKO1 outputs
384 f
S
or 768 f
S
(f
S
= 44.1 kHz) which is selected by CSEL (pin 12) for a CD-DA DSP. The output frequency of the remaining
clocks is determined by the sampling frequency (f
S
) under hardware or software control. SCKO2 and SCKO3 output 256-f
S
and 384-f
S
system clocks, respectively. Table 2 shows each sampling frequency, which can be programmed. The system
clock output frequencies for programmed sampling frequencies are shown in Table 3.
Table 1. Generated System Clock SCKO1 Frequency
CSEL
LOW
HIGH
SCKO1 FREQUENCY
33.8688 MHz
16.9344 MHz
Table 2. Sampling Frequencies
SAMPLING RATE
Standard sampling frequencies
Double sampling frequencies
SAMPLING FREQUENCY (kHz)
32
44.1
64
88.2
48
96
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PLL1720A | PHASE LOCKED LOOP |
| PLL200500 | Analog IC |
| PLL200500A | Analog IC |
| PLL20070 | Analog IC |
| PLL200730 | 3.3V/5V Low Power RS232 3-Driver/5-Receiver Transceiver; Package: SO; No of Pins: 28; Temperature Range: -40°C to +85°C |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLL1707 | 制造商:BB 制造商全稱:BB 功能描述:3.3 V DUAL PLL MULTICLOCK GENERATOR |
| PLL1707DBQ | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3 V Dual PLL Multi Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1707DBQG4 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1707DBQR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1707DBQRE4 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V Dual PLL Multi- Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。