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參數(shù)資料
| 型號： | PLHS501 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Programmable macro logic(可編程宏邏輯) |
| 中文描述： | 可編程邏輯宏（可編程宏邏輯） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 158K |
| 代理商： | PLHS501 |
Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
October 22, 1993
9
MACRO CELL SPECIFICATIONS
1
(SNAP Resource Summary Designations in Parantheses)
Commercial:T
amb
= 0
°
C to +75
°
C, 4.75V
≤
V
CC
≤
5.25V, C
L
= 30pF, R
2
= 1000
, R
1
= 470
Industrial:
T
amb
= –40
°
C to +85
°
C, 4.5V
≤
V
CC
≤
5.5V, C
L
= 30pF, R
2
= 1000
, R
1
= 470
Input Buffer
(DIN501 [Non-inverting], NIN501 [Inverting])
I
X
Y
LIMITS
TYP
SYMBOL
t
HL
t
LH
MIN
MAX
UNIT
0.05
0.1
0.15
ns/p-term
–0.02
–0.05
–0.08
ns/p-term
PARAMETER
To
(Output)
X
X
Y
Y
LIMITS
SYMBOL
From
(Input)
I
I
I
I
MIN
TYP
MAX
UNIT
NOTES
t
PHL
t
PLH
t
PHL
t
PLH
4.5
5
2.5
4
5.5
6
3
4
6.5
7.5
3.5
4.5
ns
ns
ns
ns
With 0 p-terms load
With 0 p-terms load
Input Pins: 1 – 7, 9 – 14, 41 – 45, 48 – 52.
Bidirectional Pins: 15 – 18, 37 – 40.
Maximum internal fan-out: 16 p-terms on X or Y.
NAND Output Buffer with 3-State Control
(TOU501)
Tri–Ctrl
In
Out
PARAMETER
To
(Output)
Out
Out
Out
Out
LIMITS
SYMBOL
From
(Input)
In
In
Tri-Ctrl
Tri-Ctrl
MIN
TYP
MAX
UNIT
t
PHL
t
PLH
t
OE2
t
OD2
8.5
8.5
8.5
8.5
14.0
14.0
15
12.5
17.5
16
18.5
17.0
ns
ns
ns
ns
Output Pins: 24 – 27.
Internal Foldback NAND
(FBNAND)
Output
Input
LIMITS
TYP
SYMBOL
t
PHL
t
PLH
MIN
MAX
UNIT
0.05
0.1
0.15
ns/p-term
–0.0
–0.05
–0.1
ns/p-term
PARAMETER
To
(Output)
LIMITS
SYMBOL
From
(Input)
MIN
TYP
MAX
UNIT
NOTES
t
PHL
t
PLH
Out
Any
4.0
5.5
4.5
6.5
6.8
8
ns
ns
With 0 p-terms load
Maximum internal loading of 16 terms.
Notes are on following page.
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相關代理商/技術參數(shù) |
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|---|---|
| PLHS501A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Programmable macro logic PML |
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| PLHS501IA | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Programmable macro logic PML |
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