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參數(shù)資料
| 型號： | PLHS501 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Programmable macro logic(可編程宏邏輯) |
| 中文描述： | 可編程邏輯宏（可編程宏邏輯） |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 158K |
| 代理商： | PLHS501 |
Philips Semiconductors Programmable Logic Devices
Product specification
PLHS501/PLHS501
I
Programmable macro logic
PML
October 22, 1993
10
MACRO CELL SPECIFICATIONS
1
(Continued)
(SNAP Resource Summary Designations in Parantheses)
Commercial:T
amb
= 0
°
C to +75
°
C, 4.75V
≤
V
CC
≤
5.25V, C
L
= 30pF, R
2
= 1000
, R
1
= 470
Industrial:
T
amb
= –40
°
C to +85
°
C, 4.5V
≤
V
CC
≤
5.5V, C
L
= 30pF, R
2
= 1000
, R
1
= 470
AND Output Buffer with 3-State Control
(NOU501)
Tri–Ctrl
In
Out
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
MIN
TYP
MAX
UNIT
t
PHL
t
PLH
t
OE2
t
OD2
Output
Output
In
In
8.0
8.0
11
11
13
13
ns
ns
Out
Out
Tri-Ctrl
Tri-Ctrl
8.5
8.5
15
12.5
18.5
17.0
ns
ns
Bidirectional and Output Pins: 19, 21, 22, 23, 15 – 18.
NAND Output Buffer
(OUT501)
In
Out
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
MIN
TYP
MAX
UNIT
t
PHL
t
PLH
Out
Out
In
In
8.5
8.5
14
14
17.5
16.0
ns
ns
Bidirectional Pins: 37 – 40.
Ex–OR Output Buffer
(EXO501)
Out
A
B
Tri–Ctrl
PARAMETER
LIMITS
SYMBOL
To
(Output)
From
(Input)
MIN
TYP
MAX
UNIT
t
PHL
t
PLH
t
OE2
t
OD2
Out
Out
A or B
A or B
8.5
8.5
14
14
17.5
16.0
ns
ns
Out
Out
Tri-Ctrl
Tri-Ctrl
8.5
8.5
15
12.5
18.5
17.0
ns
ns
Ex-OR Output Pins: 28 – 33.
NOTES:
1. Limits are guaranteed with internal feedback buffers simultaneously switching cumulative maximum of eight outputs.
2. For 3-State output; output enable times are tested with C
L
= 30pF to the 1.5V level, and S
1
is open for high-impedance to High tests and
closed for high-impedance to Low tests. Output disable times are tested with C
L
= 5pF. High-to-High impedance tests are made to an output
voltage of V
T
= (V
OH
– 0.5V) with S
1
open, and Low-to-High impedance tests are made to the V
T
= (V
OL
+ 0.5V) level with S
1
closed.
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相關(guān)代理商/技術(shù)參數(shù) |
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