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參數(shù)資料
| 型號(hào)： | PL-RCP-02-S53-11 |
| 廠商： | JDS UNIPHASE CORP |
| 元件分類： | 光接收 |
| 英文描述： | FIBER OPTIC RECEIVER, 830-860nm, 2700Mbps |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 495K |
| 代理商： | PL-RCP-02-S53-11 |
4
12 X 2.7 GBPS PARALLEL OPTICAL TRANSMITTER/RECEIVER
Figure 2
Transmit module block diagram
An LVCMOS logic level reset input (-Reset) is provided. A logic “1” on this pin
allows normal operation. A logic “0” on this pin will reset the laser circuitry and
disable all laser outputs. During power-up, -Reset must remain logic “0” until the
power supply (Vcc) has reached a minimum of 3V.
Receiver
The receiver converts encoded serial optical data into DC balanced parallel CML
electrical data. Receive data lines (DOUT1:DOUT12) should be terminated into
single-ended 50 loads or equivalent.
SD/SD1/-SD12
LVCMOS Signal Detect Status Outputs (SD, SD1 and -SD12) are provided. SD,
SD1 and -SD12 are independent signal detect status indicators for all channels,
channel 1, and channel 12 respectively. A logic “1” on SD indicates that sufcient
optical signal has been detected on all channels (see Section 3.5 Electrical charac-
teristics; “Signal Detect Assert/Negate Level on page 17). A logic “0” on SD indi-
cates that insufcient optical signal for proper operation has been detected on at
least one of the 12 channels. A logic “1” on SD1 and a logic “0” on -SD12 indicate
that sufcient optical signal has been detected on channels 1 and 12. A logic “0” on
SD1 and/or a logic “1” on -SD12 indicates that insufcient optical signal has been
detected at channel 1 and/or 12 for proper operation.
RXEN
An LVCMOS Receive Output Enable Input (RXEN) is provided. A logic “1” on
RXEN will enable proper operation of the high speed data outputs. A logic “0” on
RXEN powers down the outputs which leaves them xed at Vpp.
-RESET
-FAULT
TXDIS
TXEN
LASER CONTROL
LASER
DRIVER
INPUT
INTERFACE
LASER
DIODE
ARRAY
12
OPTICAL
FIBER
CONNECTOR
12
DATA
IN
VCC
VEE
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