參數(shù)資料
型號(hào): PIC24HJ32GP302-I/SO
廠商: Microchip Technology
文件頁數(shù): 31/84頁
文件大小: 0K
描述: IC PIC MCU FLASH 32K 28SOIC
標(biāo)準(zhǔn)包裝: 27
系列: PIC® 24H
核心處理器: PIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,PMP,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲(chǔ)器容量: 32KB(11K x 24)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 648 (CN2011-ZH PDF)
配用: AC164339-ND - MODULE SKT FOR PM3 28SOIC
2010 Microchip Technology Inc.
DS70152H-page 37
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
5.5
Erasing Program Memory
The procedure for erasing program memory (all of code
memory, data memory, executive memory and
code-protect bits) consists of setting NVMCON to
0x404F and then executing the programming cycle. For
segment erase operations, the NVMCON value should
be modified suitably, according to Table 5-2.
Figure 5-6 illustrates the ICSP programming process
for Bulk Erasing program memory. This process
includes the ICSP command code, which must be
transmitted (for each instruction) Least Significant bit
first, using the PGCx and PGDx pins (see Figure 5-2).
FIGURE 5-6:
BULK ERASE FLOW
If a Segment Erase operation is required, Step 3 must
be modified with the appropriate NVMCON value as
The ability to individually erase various segments is a
critical component of the CodeGuard Security
features on dsPIC33F/PIC24H devices. An individual
code segment may be erased without affecting other
segments. In addition, the Configuration register
corresponding to the erased code segment also gets
erased. For example, the user may want to erase the
code in the General Segment without erasing
a bootloader located in the Boot Segment.
The Secure Segment Erase command is used to erase
the Secure Segment and the FSS Configuration
register. The General Segment Erase command is
used to erase the General Segment and the FGS
Configuration register. This command is only effective
if a Boot Segment or Secure Segment has been
enabled.
Before performing any segment erase operation, the
programmer must first determine if the dsPIC33F/
PIC24H device has defined a Boot Segment or Secure
Segment, and ensure that a segment does not get
overwritten by operations on any other segment.
The BSS bit field in the FBS Configuration register can
be read to determine whether a Boot Segment has
been defined. If a Boot Segment has already been
defined (and probably already been programmed), the
user must be warned about this fact. Similarly, the SSS
bit field in the FSS Configuration register can be read
to determine whether a Secure Segment has been
defined. If a Secure Segment has already been defined
(and probably already been programmed), the user
must be warned about this fact.
A Bulk Erase operation is the recommended
mechanism to allow a user to overwrite the Boot
Segment (if one chooses to do so).
In
general,
the
segments
and
CodeGuard
Security-related Configuration registers should be
programmed in the following order:
FBS and Boot Segment
FSS and Secure Segment
FGS and General Segment
Note:
Program memory must be erased before
writing any data to program memory.
Start
End
Set the WR bit to Initiate Erase
Write 0x404F to NVMCON SFR
Delay P11 + P10 Time
Note 1: The
Boot
Segment
and
FBS
Configuration register can only be erased
using a Bulk Erase.
2: A Secure Segment Erase operation also
erases the General Segment and FGS
Configuration register. This is true even if
Secure Segment is present on a device
but not enabled.
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