參數(shù)資料
型號(hào): PIC24HJ32GP302-I/SO
廠商: Microchip Technology
文件頁(yè)數(shù): 29/84頁(yè)
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 32K 28SOIC
標(biāo)準(zhǔn)包裝: 27
系列: PIC® 24H
核心處理器: PIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,PMP,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲(chǔ)器容量: 32KB(11K x 24)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 648 (CN2011-ZH PDF)
配用: AC164339-ND - MODULE SKT FOR PM3 28SOIC
2010 Microchip Technology Inc.
DS70152H-page 35
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
5.4
Flash Memory Programming in
ICSP Mode
5.4.1
PROGRAMMING OPERATIONS
Flash memory write and erase operations are
controlled by the NVMCON register. Programming is
performed by setting NVMCON to select the type of
erase operation (Table 5-2) or write operation
(Table 5-3) and initiating the programming by setting
the WR control bit (NVMCON<15>).
In ICSP mode, all programming operations are
self-timed. There is an internal delay between the user
setting the WR control bit and the automatic clearing of
the WR control bit when the programming operation is
complete. Please refer to Section 8.0 “AC/DC
detailed information about the delays associated with
various programming operations.
TABLE 5-2:
NVMCON ERASE OPERATIONS
TABLE 5-3:
NVMCON WRITE OPERATIONS
5.4.2
STARTING AND STOPPING A
PROGRAMMING CYCLE
The WR bit (NVMCON<15>) is used to start an erase
or write cycle. Setting the WR bit initiates the
programming cycle.
All erase and write cycles are self-timed. The WR bit
should be polled to determine if the erase or write cycle
has been completed. Starting a programming cycle is
performed as follows:
BSET
NVMCON, #WR
FIGURE 5-5:
ENTERING ICSP MODE
NVMCON
Value
Erase Operation
0x404F
Erase all code memory, executive
memory and CodeGuard Configuration
registers (does not erase Unit ID or
Device ID registers).
0x404D
Erase General Segment and FGS
Configuration register.
0x404C
Erase Secure Segment and FSS
Configuration register. This operation will
also erase the General Segment and
FGS Configuration register.
0x4042
Erase a page of code memory or
executive memory.
NVMCON
Value
Write Operation
0x4001
Program 1 row (64 instruction words)
of code memory or executive memory.
0x4000
Write a Configuration register byte.
0x4003
Program a code memory word.
MCLR
PGDx
PGCx
VDD
P6
P14
b31 b30 b29
b28
b27
b2
b1
b0
b3
...
Program/Verify Entry Code = 0x4D434851
P1A
P1B
P18
P19
0
1
001
0
1
P7
VIH
P21
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