參數(shù)資料
型號: PIC24FJ64GA006-I/PT
廠商: Microchip Technology
文件頁數(shù): 200/258頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 64KB 64TQFP
產(chǎn)品培訓(xùn)模塊: PIC24 Introduction
Graphics LCD System and PIC24 Interface
Asynchronous Stimulus
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標(biāo)準(zhǔn)包裝: 160
系列: PIC® 24F
核心處理器: PIC
芯體尺寸: 16-位
速度: 16MHz
連通性: I²C,PMP,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲器容量: 64KB(22K x 24)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 647 (CN2011-ZH PDF)
配用: DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
MA160011-ND - DAUGHTER BOARD PICDEM LCD 16F91X
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
AC164327-ND - MODULE SKT FOR 64TQFP
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PIC24FJ128GA010 FAMILY
DS39747F-page 46
2005-2012 Microchip Technology Inc.
4.2.5
SOFTWARE STACK
In addition to its use as a working register, the W15 reg-
ister in PIC24F devices is also used as a Software
Stack Pointer. The pointer always points to the first
available free word and grows from lower to higher
addresses. It predecrements for stack pops and post-
increments for stack pushes, as shown in Figure 4-4.
Note that for a PC push during any CALL instruction,
the MSB of the PC is zero-extended before the push,
ensuring that the MSB is always clear.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word-aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is com-
pared with the value in SPLIM. If the contents of the
Stack Pointer (W15) and the SPLIM register are equal
and a push operation is performed, a stack error trap
will not occur. The stack error trap will occur on a
subsequent push operation. Thus, for example, if it is
desirable to cause a stack error trap when the stack
grows beyond address, 2000h, in RAM, initialize the
SPLIM with the value, 1FFEh.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0800h. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-4:
CALL
STACK FRAME
4.3
Interfacing Program and Data
Memory Spaces
The PIC24F architecture uses a 24-bit wide program
space and 16-bit wide data space. The architecture is
also a modified Harvard scheme, meaning that data
can also be present in the program space. To use this
data successfully, it must be accessed in a way that
preserves the alignment of information in both spaces.
Aside from normal execution, the PIC24F architecture
provides two methods by which program space can be
accessed during operation:
Using table instructions to access individual bytes
or words anywhere in the program space
Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This makes the
method ideal for accessing data tables that need to be
updated from time to time. It also allows access to all
bytes of the program word. The remapping method
allows an application to access a large block of data on
a read-only basis, which is ideal for look ups from a
large table of static data. It can only access the least
significant word of the program word.
4.3.1
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determine if the operation occurs in the user memory
(TBLPAG<7> = 0) or the configuration memory
(TBLPAG<7> = 1).
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the Most
Significant bit of the EA is ‘1’, PSVPAG is concatenated
with the lower 15 bits of the EA to form a 23-bit program
space address. Unlike table operations, this limits
remapping operations strictly to the user memory area.
Table 4-31 and Figure 4-5 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word, whereas D<15:0> refers to a data space
word.
Note:
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
<Free Word>
PC<15:0>
000000000
0
15
W15 (before CALL)
W15 (after CALL)
S
tac
kG
row
sT
o
w
a
rd
s
Highe
rA
ddr
es
s
0000h
PC<22:16>
POP
: [--W15]
PUSH : [W15++]
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