參數(shù)資料
型號(hào): PIC18LF24J10T-I/ML
廠商: Microchip Technology
文件頁數(shù): 63/80頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 8KX16 28QFN
標(biāo)準(zhǔn)包裝: 1
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲(chǔ)器容量: 16KB(8K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 剪切帶 (CT)
配用: AC162074-ND - HEADER INTRFC MPLAB ICD2 44TQFP
MA180012-ND - MODULE PLUG-IN 18LF25J10 28SOIC
AC162067-ND - HEADER INTRFC MPLAB ICD2 40/28P
其它名稱: PIC18LF24J10T-I/MLCT
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
66
M9999-083109-2.0
Port 1 Control Register (0xF6 – 0xF7): P1CR
This register contains the global per port control for the chip function.
Bit
Default
R/W
Description
Bit is same as:
15
0
RW
LED Off
1 = Turn off all of the port 1 LEDs (P1LED3, P1LED2,
P1LED1, P1LED0). These pins are driven high if this bit is
set to one.
0 = normal operation.
Bit 0 in P1MBCR
14
0
RW
Txids
1 = disable the port’s transmitter.
0 = normal operation.
Bit 1 in P1MBCR
13
0
RW
Restart AN
1 = restart auto-negotiation.
0 = normal operation.
Bit 9 in P1MBCR
12
0
RW
Reserved
11
0
RW
Reserved
10
0
RW
Disable auto MDI/MDI-X
1 = disable auto MDI/MDI-X function.
0 = enable auto MDI/MDI-X function.
Bit 3 in P1MBCR
9
0
RW
Force MDI-X
1= if auto MDI/MDI-X is disabled, force PHY into MDI-X
mode.
0 = do not force PHY into MDI-X mode.
Bit 4 in P1MBCR
8
0
RW
Reserved
7
1
RW
Auto Negotiation Enable
1 = auto negotiation is enabled.
0 = disable auto negotiation, speed, and duplex are decided
by bits 6 and 5 of the same register.
Bit 12 in P1MBCR
6
1
RW
Force Speed
1 = force 100BT if AN is disabled (bit 7).
0 = force 10BT if AN is disabled (bit 7).
Bit 13 in P1MBCR
5
1
RW
Force Duplex
1 = force full duplex if (1) AN is disabled or (2) AN is
enabled but failed.
0 = force half duplex if (1) AN is disabled or (2) AN is
enabled but failed.
Bit 8 in P1MBCR
4
1
RW
Advertised flow control capability.
1 = advertise flow control (pause) capability.
0 = suppress flow control (pause) capability from
transmission to link partner.
Bit 10 in P1ANAR
3
1
RW
Advertised 100BT full-duplex capability.
1 = advertise 100BT full-duplex capability.
0 = suppress 100BT full-duplex capability from transmission
to link partner.
Bit 8 in P1ANAR
2
1
RW
Advertised 100BT half-duplex capability.
1 = advertise 100BT half-duplex capability.
0 = suppress 100BT half-duplex capability from transmission
to link partner.
Bit 7 in P1ANAR
1
RW
Advertised 10BT full-duplex capability.
Bit 6 in P1ANAR
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