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| 型號(hào)： | PIC18F86J60 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 64/80/100-Pin, High-Performance, 1 Mbit Flash Microcontrollers with Ethernet |
| 中文描述： | 64/80/100-Pin，高性能，1兆位閃存微控制器與以太網(wǎng) |
| 文件頁(yè)數(shù)： | 361/474頁(yè) |
| 文件大?。?/td> | 3834K |
| 代理商： | PIC18F86J60 |
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2006 Microchip Technology Inc.
Advance Information
DS39762A-page 359
PIC18F97J60 FAMILY
25.0
INSTRUCTION SET SUMMARY
The PIC18F97J60 family of devices incorporates the
standard set of 75 PIC18 core instructions, as well as
an extended set of 8 new instructions for the optimiza-
tion of code that is recursive or that utilizes a software
stack. The extended set is discussed later in this
section.
25.1
Standard Instruction Set
The standard PIC18 instruction set adds many
enhancements to the previous PICmicro
instruction
sets, while maintaining an easy migration from these
PICmicro instruction sets. Most instructions are a
single program memory word (16 bits), but there are
four instructions that require two program memory
locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
Byte-oriented
operations
Bit-oriented
operations
Literal
operations
Control
operations
The PIC18 instruction set summary in Table 25-2 lists
byte-oriented
,
bit-oriented
,
literal
and
control
operations. Table 25-1 shows the opcode field
descriptions.
Most
byte-oriented
instructions have three operands:
1.
2.
3.
The file register (specified by ‘f’)
The destination of the result (specified by ‘d’)
The accessed memory (specified by ‘a(chǎn)’)
The file register designator ‘f’ specifies which file regis-
ter is to be used by the instruction. The destination
designator ‘d’ specifies where the result of the
operation is to be placed. If ‘d’ is zero, the result is
placed in the WREG register. If ‘d’ is one, the result is
placed in the file register specified in the instruction.
All
bit-oriented
instructions have three operands:
1.
2.
3.
The file register (specified by ‘f’)
The bit in the file register (specified by ‘b’)
The accessed memory (specified by ‘a(chǎn)’)
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register desig-
nator ‘f’ represents the number of the file in which the
bit is located.
The
literal
instructions may use some of the following
operands:
A literal value to be loaded into a file register
(specified by ‘k’)
The desired FSR register to load the literal value
into (specified by ‘f’)
No operand required
(specified by ‘—’)
The
control
instructions may use some of the following
operands:
A program memory address (specified by ‘n’)
The mode of the
CALL
or
RETURN
instructions
(specified by ‘s’)
The mode of the table read and table write
instructions (specified by ‘m’)
No operand required
(specified by ‘—’)
All instructions are a single word, except for four
double-word instructions. These instructions were
made double-word to contain the required information
in 32 bits. In the second word, the 4 MSbs are ‘
1
’s. If
this second word is executed as an instruction (by
itself), it will execute as a
NOP
.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a
NOP
.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1
μ
s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2
μ
s.
Two-word branch instructions (if true) would take 3
μ
s.
Figure 25-1 shows the general formats that the instruc-
tions can have. All examples use the convention ‘nnh’
to represent a hexadecimal number.
The Instruction Set Summary, shown in Table 25-2,
lists the standard instructions recognized by the
Microchip MPASM
TM
Assembler.
Section 25.1.1 “Standard Instruction Set”
provides
a description of each instruction.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| PIC18F86J60-I/PT | 功能描述:8位微控制器 -MCU 64KB FL 12KB RAM 10BASE-T RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC18F86J60T-I/PT | 功能描述:8位微控制器 -MCU 64KB FL 12KB RAM 10BASE-T RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC18F86J65-I/PT | 功能描述:8位微控制器 -MCU 96KB FL 12KB RAM 10BASE-T RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC18F86J65T-I/PT | 功能描述:8位微控制器 -MCU 96KB FL 12KB RAM 10BASE-T RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC18F86J72-I/PT | 功能描述:8位微控制器 -MCU Energy Meter 64KB LCD, CTMU, RTCC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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