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    參數資料
    型號: PIC18F86J55T-I/PT
    廠商: Microchip Technology
    文件頁數: 27/61頁
    文件大?。?/td> 0K
    描述: IC PIC MCU FLASH 48KX16 80TQFP
    產品培訓模塊: Asynchronous Stimulus
    PIC18 J Series MCU Overview
    標準包裝: 1,200
    系列: PIC® 18F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 48MHz
    連通性: EBI/EMI,I²C,SPI,UART/USART,USB
    外圍設備: 欠壓檢測/復位,LVD,POR,PWM,WDT
    輸入/輸出數: 65
    程序存儲器容量: 96KB(48K x 16)
    程序存儲器類型: 閃存
    RAM 容量: 3.8K x 8
    電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
    數據轉換器: A/D 12x10b
    振蕩器型: 內部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 80-TQFP
    包裝: 帶卷 (TR)
    配用: AC162087-ND - HEADER MPLAB ICD2 18F87J50 68/84
    MA180021-ND - MODULE PLUG-IN 18F87J50 FS USB
    AC164328-ND - MODULE SKT FOR 80TQFP
    其它名稱: PIC18F86J55T-I/PTTR
    Philips Semiconductors
    Product data
    P87LPC767
    Low power, low price, low pin count (20 pin)
    microcontroller with 4-kbyte OTP and 8-bit A/D converter
    2002 Mar 25
    30
    Low Voltage EPROM Operation
    The EPROM array contains some analog circuits that are not
    required when VDD is less than 4 V, but are required for a VDD
    greater than 4 V. The LPEP bit (AUXR.4), when set by software, will
    power down these analog circuits resulting in a reduced supply
    current. LPEP is cleared only by power-on reset, so it may be set
    ONLY for applications that always operate with VDD less than 4 V.
    Reset
    The P87LPC767 has an integrated power-on reset circuit which
    always provides a reset when power is initially applied to the device.
    It is recommended to use the internal reset whenever possible to
    save external components and to be able to use pin P1.5 as a
    general-purpose input pin.
    The P87LPC767 can additionally be configured to use P1.5 as an
    external active-low reset pin RST by programming the RPD bit in the
    User Configuration Register UCFG1 to 0. The internal reset is still
    active on power-up of the device. While the signal on the RST pin is
    low, the P87LPC767 is held in reset until the signal goes high.
    The watchdog timer on the P87LPC767 can act as an oscillator fail
    detect because it uses an independent, fully on-chip oscillator.
    UCFG1 is described in the System Configuration Bytes section of
    this datasheet.
    SU01359
    87LPC767
    P1.5
    Pin is used as
    digital input pin
    Internal power-on
    Reset active
    UCFG1.RPD = 1 (default)
    RST
    Pin is used as
    active-low reset pin
    Internal power-on
    Reset active
    UCFG1.RPD = 0
    Figure 22. Using pin P1.5 as general purpose input pin or as low-active reset pin
    SU01170
    CHIP RESET
    CPU
    CLOCK
    Q
    RESET
    TIMING
    RPD (UCFG1.6)
    WDT
    MODULE
    SOFTWARE RESET
    SRST (AUXR1.3)
    POWER MONITOR
    RESET
    RST/VPP PIN
    WDTE (UCFG1.7)
    S
    R
    Figure 23. Block Diagram Showing Reset Sources
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