參數(shù)資料
型號(hào)： PIC18F85J50T-I/PT
廠商： Microchip Technology
文件頁(yè)數(shù)： 44/61頁(yè)
文件大小： 0K
描述： IC PIC MCU FLASH 16KX16 80TQFP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
PIC18 J Series MCU Overview
標(biāo)準(zhǔn)包裝： 1,200
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 48MHz
連通性： EBI/EMI，I²C，SPI，UART/USART，USB
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 65
程序存儲(chǔ)器容量： 32KB（16K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 3.8K x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-TQFP
包裝： 帶卷 (TR)
配用： AC162087-ND - HEADER MPLAB ICD2 18F87J50 68/84
MA180021-ND - MODULE PLUG-IN 18F87J50 FS USB
AC164328-ND - MODULE SKT FOR 80TQFP
其它名稱： PIC18F85J50T-I/PTTR
Philips Semiconductors
Product data
P87LPC767
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
2002 Mar 25
46
Additional Features
The AUXR1 register contains several special purpose control bits that
relate to several chip features. AUXR1 is described in Figure 37.
Software Reset
The SRST bit in AUXR1 allows software the opportunity to reset the
processor completely, as if an external reset or watchdog reset had
occurred. If a value is written to AUXR1 that contains a 1 at bit
position 3, all SFRs will be initialized and execution will resume at
program address 0000. Care should be taken when writing to
AUXR1 to avoid accidental software resets.
Dual Data Pointers
The dual Data Pointer (DPTR) adds to the ways in which the
processor can specify the address used with certain instructions.
The DPS bit in the AUXR1 register selects one of the two Data
Pointers. The DPTR that is not currently selected is not accessible
to software unless the DPS bit is toggled.
Specific instructions affected by the Data Pointer selection are:
INC DPTR
Increments the Data Pointer by 1.
JMP @A+DPTR
Jump indirect relative to DPTR value.
MOV DPTR, #data16 Load the Data Pointer with a 16-bit
constant.
MOVC A, @A+DPTR Move code byte relative to DPTR to the
accumulator.
MOVX A, @DPTR
Move data byte the accumulator to data
memory relative to DPTR.
MOVX @DPTR, A
Move data byte from data memory
relative to DPTR to the accumulator.
Also, any instruction that reads or manipulates the DPH and DPL
registers (the upper and lower bytes of the current DPTR) will be
affected by the setting of DPS. The MOVX instructions have limited
application for the P87LPC767 since the part does not have an
external data bus. However, they may be used to access EPROM
configuration information (see EPROM Characteristics section).
Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the
DPS bit may be toggled (thereby switching Data Pointers) simply by
incrementing the AUXR1 register, without the possibility of
inadvertently altering other bits in the register.
BIT
SYMBOL
FUNCTION
AUXR1.7
KBF
Keyboard Interrupt Flag. Set when any pin of port 0 that is enabled for the Keyboard Interrupt
function goes low. Must be cleared by software.
AUXR1.6
BOD
Brown Out Disable. When set, turns off brownout detection and saves power. See Power
Monitoring Functions section for details.
AUXR1.5
BOI
Brown Out Interrupt. When set, prevents brownout detection from causing a chip reset and allows
the brownout detect function to be used as an interrupt. See the Power Monitoring Functions
section for details.
AUXR1.4
LPEP
Low Power EPROM control bit. Allows power savings in low voltage systems. Set by software. Can
only be cleared by power-on or brownout reset. See the Power Reduction Modes section for
details.
AUXR1.3
SRST
Software Reset. When set by software, resets the P87LPC767 as if a hardware reset occurred.
AUXR1.2
—
This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1, without
interfering with other bits in the register.
AUXR1.1
—
Reserved for future use. Should not be set to 1 by user programs.
AUXR1.0
DPS
Data Pointer Select. Chooses one of two Data Pointers for use by the program. See text for details.
DPS
SU01639
—
0
SRST
LPEP
BOI
BOD
KBF
0
1
2
3
4
5
6
7
AUXR1
Reset Value: 00h
Not Bit Addressable
Address: A2h
Figure 37. AUXR1 Register
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