2003 Microchip Technology Inc.
Advance Information
DS39612A-page 231
PIC18F6X2X/8X2X
19.3.2
USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTAx<5>), or the Continuous Receive
Enable bit, CREN (RCSTAx<4>). Data is sampled on
the RXx pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1.
Initialize the SPBRGHx:SPBRGx registers for
the appropriate baud rate. Set or clear the
BRG16 bit, as required, to achieve the desired
baud rate.
2.
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3.
4.
5.
6.
Ensure bits CREN and SREN are clear.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
7.
8.
9.
FIGURE 19-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 19-8:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
INTCON
PIR1
PIE1
IPR1
RCSTAx
RCREGx
TXSTAx
BAUDCONx
SPBRGHx
SPBRGx
Legend:
GIE/GIEH PEIE/GIEL
—
—
—
SPEN
USART Receive Register
CSRC
—
Baud Rate Generator Register, High Byte
Baud Rate Generator Register, Low Byte
x
= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
TMR0IE
RCIF
RCIE
RCIP
SREN
INT0IE
TXIF
TXIE
TXIP
CREN
RBIE
—
—
—
ADDEN
TMR0IF
CCP1IF
CCP1IE
CCP1IP
FERR
INT0IF
TMR2IF
TMR2IE
TMR2IP
OERR
RBIF
TMR1IF
TMR1IE
TMR1IP
RX9D
0000 0000
0000 0000
ADIF
ADIE
ADIP
RX9
0000 -000
0000 -000
0000 -000
0000 -000
1111 1111
1111 1111
0000 000x
0000 000x
0000 0000
0000 0000
TX9
RCIDL
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
ABDEN
0000 0010
0000 0010
-1-0 0-00
-1-0 0-00
0000 0000
0000 0000
0000 0000
0000 0000
CREN bit
RC7/RX1/pin
RC7/TX1/CK1 pin
(SCKP =
0
)
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q2
Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1Q2 Q3 Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4 Q1 Q2 Q3 Q4
‘0’
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
‘0’
Q1 Q2 Q3 Q4
Note:
Timing diagram demonstrates Sync Master mode with bit SREN =
1
and bit BRGH =
0
.
RC7/TX1/CK1 pin
(SCKP =
1
)