參數(shù)資料
型號: PIC18F8525-EPTQTP
廠商: Microchip Technology Inc.
英文描述: 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D
中文描述: 64/80-Pin高性能,64字節(jié)的閃存微控制器與A /數(shù)
文件頁數(shù): 149/386頁
文件大?。?/td> 3107K
代理商: PIC18F8525-EPTQTP
2003 Microchip Technology Inc.
Advance Information
DS39612A-page 147
PIC18F6X2X/8X2X
14.2
Timer1 Oscillator
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a low
power oscillator rated up to 200 kHz. See Section 12.0
for further details.
14.3
Timer3 Interrupt
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled/disabled by
setting/clearing TMR3 interrupt enable bit, TMR3IE
(PIE2<1>).
14.4
Resetting Timer3 Using an ECCP
Special Trigger Output
If either the ECCP1 or ECCP2 module is configured in
Compare mode to generate a special event trigger
(CCP1M3:CCP1M0 =
1011
), this signal will reset
Timer3.
Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this RESET operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from ECCP1, the write will take precedence. In this
mode of operation, the CCPR1H:CCPR1L register pair
effectively becomes the period register for Timer3.
TABLE 14-1:
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Note:
The special event triggers from the CCP
module will not set interrupt flag bit,
TMR3IF (PIR1<0>).
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
INTCON
GIE/
GIEH
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
PEIE/
GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 0000
0000 0000
PIR2
PIE2
IPR2
TMR3L
TMR3H
EEIF
EEIE
EEIP
BCLIF
BCLIE
BCLIP
LVDIF
LVDIE
LVDIP
TMR3IF
TMR3IE
TMR3IP
CCP2IF
CCP2IE
CCP2IP
---0 0000
---0 0000
---0 0000
---0 0000
---1 1111
---1 1111
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
T1CON
RD16
T1CKPS1 T1CKPS0 T1OSCEN
T1SYNC
TMR1CS
TMR1ON
0-00 0000
u-uu uuuu
T3CON
Legend:
RD16
x
= unknown,
u
= unchanged,
-
= unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
T3CCP2
T3CKPS1 T3CKPS0
T3CCP1
T3SYNC
TMR3CS
TMR3ON
0000 0000
uuuu uuuu
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PIC18F8525-EPTSQTP 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D
PIC18F8525-IPTQTP 64/80-Pin High Performance, 64-Kbyte Enhanced FLASH Microcontrollers with A/D
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