2010 Microchip Technology Inc.
DS39774D-page 205
PIC18F85J11 FAMILY
FIGURE 17-16:
I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESSING)
SDA
SCL
S
P
IF
(P
IR
1<
3>
)
BF
(
S
PST
A
T
<
0>)
S
1
2
34
56
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
7
8
9
P
1
0
A
9
A
8
A
7
A
6
A
5
A
4A
3A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
1
D
0
Re
ce
ive
Da
ta
B
yt
e
ACK
R/W
=
0
ACK
R
e
cei
ve
F
irst
B
yte
of
A
ddre
ss
Cl
ea
re
din
so
ftwa
re
D2
6
Cle
a
re
d
in
so
ftwa
re
R
e
cei
ve
S
e
co
nd
B
yte
of
A
ddress
C
le
a
red
by
har
dw
ar
e
w
hen
S
P
A
DD
is
u
p
da
te
d
with
lo
w
byte
of
addr
ess
af
ter
falling
e
d
ge
UA
(
SSP
ST
A
T
<1
>)
Clo
ck
is
h
e
ld
lo
w
u
n
til
update
of
S
P
A
D
h
a
s
ta
ke
n
pl
ace
U
A
is
set
indi
cati
ng
that
the
S
P
A
D
n
eeds
to
be
update
d
UA
is
set
indicat
in
g
tha
t
S
P
A
D
ne
eds
to
be
upda
ted
C
lear
ed
by
hard
w
a
re
w
hen
SS
P
A
DD
is
u
p
d
a
te
d
with
h
ig
h
byte
of
ad
dress
af
ter
fa
lli
ng
edg
e
SS
PBU
F
is
wr
itte
n
with
conte
n
ts
of
S
P
S
R
Du
m
yr
e
ad
o
fSSP
BUF
to
clea
rB
F
flag
AC
K
CKP
(
S
P
CON1
<4
>)
12
3
4
5
7
8
9
D7
D6
D5
D4
D3
D1
D0
Re
ce
ive
Da
ta
B
yte
B
u
sm
a
ster
term
in
ates
transf
e
r
D2
6
ACK
Cle
ar
e
din
so
ftwa
re
Cl
ea
re
din
so
ftwa
re
SSP
O
V
(
S
SPCO
N
1
<
6
>
)
CK
P
written
to
‘1
’
No
te
:
A
n
update
of
the
S
P
A
D
regi
ster
bef
o
re
the
fa
llin
g
e
d
ge
o
fth
e
n
in
th
cl
ock
will
h
a
ve
n
o
e
ffe
ct
o
nUA
a
n
d
UA
will
r
e
m
a
in
se
t.
No
te
:
A
n
upda
te
of
the
S
P
A
D
registe
rb
e
for
e
th
efa
llin
g
edge
of
the
ninth
clock
will
have
n
o
ef
fe
ct
on
U
A
an
d
UA
will
r
em
a
in
se
t.
in
so
ftwa
re
Clo
ck
is
h
e
ld
lo
w
u
n
til
upda
te
of
S
P
A
D
has
ta
ken
p
lace
of
ni
nth
cl
ock
of
ni
nth
cl
ock
S
P
OV
is
set
be
cause
S
P
B
U
F
is
still
fu
ll.
A
C
K
is
not
sent.
D
ummy
r
ead
of
S
P
B
U
F
to
clear
B
F
flag
Clo
ck
is
h
e
ld
lo
w
u
ntil
CKP
is
se
tto
‘1
’
C
lo
ck
is
n
o
th
e
ld
lo
w
because
A
C
K
=
1