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PIC18F87J50 FAMILY
DS39775B-page 472
Preliminary
2007 Microchip Technology Inc.
EUSARTx Synchronous Transmission
(Master/Slave) ..................................................453
Example SPI Master Mode (CKE = 0) .....................445
Example SPI Master Mode (CKE = 1) .....................446
Example SPI Slave Mode (CKE = 0) .......................447
Example SPI Slave Mode (CKE = 1) .......................448
External Clock ..........................................................435
External Memory Bus for SLEEP
(Extended Microcontroller Mode) .............112, 114
External Memory Bus for TBLRD
(Extended Microcontroller Mode) .............112, 114
Fail-Safe Clock Monitor ............................................361
First Start Bit Timing ................................................265
Full-Bridge PWM Output ..........................................223
Half-Bridge PWM Output .........................................222
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2
C Acknowledge Sequence ....................................270
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2
C Bus Data ............................................................449
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2
C Bus Start/Stop Bits .............................................449
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2
C Master Mode (7 or 10-Bit Transmission) ...........268
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2
C Master Mode (7-Bit Reception) ..........................269
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2
C Slave Mode (10-Bit Reception, SEN = 0) ..........254
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2
C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001) .............................................253
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2
C Slave Mode (10-Bit Reception, SEN = 1) ..........259
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2
C Slave Mode (10-Bit Transmission) .....................255
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2
C Slave Mode (7-Bit Reception, SEN = 0) ............250
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2
C Slave Mode (7-Bit Reception, SEN = 0,
ADMSK = 01011) .............................................251
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2
C Slave Mode (7-Bit Reception, SEN = 1) ............258
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2
C Slave Mode (7-Bit Transmission) .......................252
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2
C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) .............260
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2
C Stop Condition Receive or Transmit Mode ........270
MSSPx I
2
C Bus Data ...............................................451
MSSPx I
2
C Bus Start/Stop Bits ................................451
Parallel Master Port Read ........................................443
Parallel Master Port Write ........................................444
Parallel Slave Port Read ..................................174, 177
Parallel Slave Port Write ..................................174, 177
Program Memory Read ............................................438
Program Memory Write ............................................439
PWM Auto-Shutdown (P1RSEN = 0,
Auto-Restart Disabled) .....................................228
PWM Auto-Shutdown (P1RSEN = 1,
Auto-Restart Enabled) .....................................228
PWM Direction Change ...........................................225
PWM Direction Change at Near
100% Duty Cycle .............................................225
PWM Output ............................................................212
Read and Write, 8-Bit Data,
Demultiplexed Address ....................................181
Read, 16-Bit Data, Demultiplexed Address .............184
Read, 16-Bit Multiplexed Data, Fully
Multiplexed 16-Bit Address ..............................185
Read, 16-Bit Multiplexed Data, Partially
Multiplexed Address .........................................184
Read, 8-Bit Data, Fully Multiplexed
16-Bit Address .................................................183
Read, 8-Bit Data, Partially Multiplexed Address ......181
Read, 8-Bit Data, Partially Multiplexed Address,
Enable Strobe ..................................................182
Read, 8-Bit Data, Wait States Enabled,
Partially Multiplexed Address ...........................181
Repeated Start Condition .........................................266
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ..... 440
Send Break Character Sequence ............................ 292
Slave Synchronization ............................................. 237
Slow Rise Time (MCLR Tied to V
DD
,
V
DD
Rise > T
PWRT
) ............................................ 57
SPI Mode (Master Mode) ......................................... 236
SPI Mode (Slave Mode, CKE = 0) ........................... 238
SPI Mode (Slave Mode, CKE = 1) ........................... 238
Synchronous Reception (Master Mode, SREN) ...... 295
Synchronous Transmission ..................................... 293
Synchronous Transmission (Through TXEN) .......... 294
Time-out Sequence on Power-up
(MCLR Not Tied to V
DD
), Case 1 ...................... 56
Time-out Sequence on Power-up
(MCLR Not Tied to V
DD
), Case 2 ...................... 57
Time-out Sequence on Power-up
(MCLR Tied to V
DD
, V
DD
Rise < T
PWRT
) ........... 56
Timer0 and Timer1 External Clock .......................... 441
Transition for Entry to Idle Mode ................................ 50
Transition for Entry to SEC_RUN Mode .................... 47
Transition for Entry to Sleep Mode ............................ 49
Transition for Two-Speed Start-up
(INTRC to HSPLL) ........................................... 359
Transition for Wake From Idle to Run Mode .............. 50
Transition for Wake From Sleep (HSPLL) ................. 49
Transition From RC_RUN Mode to
PRI_RUN Mode ................................................. 48
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 47
Transition to RC_RUN Mode ..................................... 48
USB Signal .............................................................. 456
Write, 16-Bit Data, Demultiplexed Address ............. 184
Write, 16-Bit Multiplexed Data, Fully
Multiplexed 16-Bit Address .............................. 185
Write, 16-Bit Multiplexed Data, Partially
Multiplexed Address ........................................ 185
Write, 8-Bit Data, Fully Multiplexed
16-Bit Address ................................................. 183
Write, 8-Bit Data, Partially Multiplexed Address ...... 182
Write, 8-Bit Data, Partially Multiplexed
Address, Enable Strobe ................................... 183
Write, 8-Bit Data, Wait States Enabled,
Partially Multiplexed Address .......................... 182
Timing Diagrams and Specifications
AC Characteristics
Internal RC Accuracy ....................................... 436
Capture/Compare/PWM Requirements
(Including ECCP Modules) .............................. 442
CLKO and I/O Requirements ................................... 437
EUSARTx Synchronous Receive
Requirements .................................................. 453
EUSARTx Synchronous Transmission
Requirements .................................................. 453
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 445
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 446
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 447
Example SPI Slave Mode
Requirements (CKE = 1) ................................. 448
External Clock Requirements .................................. 435
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C Bus Data Requirements (Slave Mode) .............. 450