PIC18F87J50 FAMILY
DS39775B-page 466
Preliminary
2007 Microchip Technology Inc.
F
Fail-Safe Clock Monitor ............................................347, 360
Interrupts in Power-Managed Modes .......................361
POR or Wake-up From Sleep ..................................361
WDT During Oscillator Failure .................................360
Fast Register Stack ............................................................73
Firmware Instructions .......................................................363
Flash Configuration Words ...............................................347
Flash Program Memory ......................................................95
Associated Registers ...............................................104
Control Registers .......................................................96
EECON1 and EECON2 .....................................96
TABLAT (Table Latch) Register .........................98
TBLPTR (Table Pointer) Register ......................98
Erase Sequence ......................................................100
Erasing .....................................................................100
Operation During Code-Protect ...............................104
Reading ......................................................................99
Table Pointer
Boundaries Based on Operation ........................98
Table Pointer Boundaries ..........................................98
Table Reads and Table Writes ..................................95
Write Sequence .......................................................101
Writing ......................................................................101
Unexpected Termination ..................................104
Write Verify ......................................................104
FSCM.
See
Fail-Safe Clock Monitor.
G
GOTO ...............................................................................384
H
Hardware Multiplier ..........................................................117
8 x 8 Multiplication Algorithms .................................117
Operation .................................................................117
Performance Comparison (table) .............................117
I
I/O Ports ...........................................................................135
Input Pull-up Configuration ......................................136
Open-Drain Outputs .................................................136
Pin Capabilities ........................................................135
TTL Input Buffer Option ...........................................136
I
2
C Mode (MSSP)
Acknowledge Sequence Timing ...............................270
Associated Registers ...............................................276
Baud Rate Generator ...............................................263
Bus Collision
During a Repeated Start Condition ..................274
During a Stop Condition ...................................275
Clock Arbitration .......................................................264
Clock Stretching .......................................................256
10-Bit Slave Receive Mode (SEN = 1) .............256
10-Bit Slave Transmit Mode .............................256
7-Bit Slave Receive Mode (SEN = 1) ...............256
7-Bit Slave Transmit Mode ...............................256
Clock Synchronization and the CKP bit ...................257
Effects of a Reset .....................................................271
General Call Address Support .................................260
I
2
C Clock Rate w/BRG .............................................263
Master Mode ............................................................261
Operation .........................................................262
Reception .........................................................267
Repeated Start Condition Timing .....................266
Start Condition Timing .....................................265
Transmission ....................................................267
Multi-Master Communication, Bus Collision
and Arbitration ................................................. 271
Multi-Master Mode ................................................... 271
Operation ................................................................. 246
Read/Write Bit Information (R/W Bit) ............... 246, 249
Registers ................................................................. 241
Serial Clock (RC3/SCKx/SCLx) ............................... 249
Slave Mode .............................................................. 246
Addressing ....................................................... 246
Addressing Masking Modes
5-Bit ......................................................... 247
7-Bit ......................................................... 248
Reception ........................................................ 249
Transmission ................................................... 249
Sleep Operation ....................................................... 271
Stop Condition Timing ............................................. 270
INCF ................................................................................ 384
INCFSZ ............................................................................ 385
In-Circuit Debugger .......................................................... 362
In-Circuit Serial Programming (ICSP) ...................... 347, 362
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 410
Indexed Literal Offset Mode ............................................. 410
Indirect Addressing ............................................................ 89
INFSNZ ............................................................................ 385
Initialization Conditions for All Registers ...................... 59–65
Instruction Cycle ................................................................ 74
Clocking Scheme ....................................................... 74
Flow/Pipelining ........................................................... 74
Instruction Set .................................................................. 363
ADDLW .................................................................... 369
ADDWF .................................................................... 369
ADDWF (Indexed Literal Offset Mode) .................... 411
ADDWFC ................................................................. 370
ANDLW .................................................................... 370
ANDWF .................................................................... 371
BC ............................................................................ 371
BCF ......................................................................... 372
BN ............................................................................ 372
BNC ......................................................................... 373
BNN ......................................................................... 373
BNOV ...................................................................... 374
BNZ ......................................................................... 374
BOV ......................................................................... 377
BRA ......................................................................... 375
BSF .......................................................................... 375
BSF (Indexed Literal Offset Mode) .......................... 411
BTFSC ..................................................................... 376
BTFSS ..................................................................... 376
BTG ......................................................................... 377
BZ ............................................................................ 378
CALL ........................................................................ 378
CLRF ....................................................................... 379
CLRWDT ................................................................. 379
COMF ...................................................................... 380
CPFSEQ .................................................................. 380
CPFSGT .................................................................. 381
CPFSLT ................................................................... 381
DAW ........................................................................ 382
DCFSNZ .................................................................. 383
DECF ....................................................................... 382
DECFSZ .................................................................. 383
Extended Instructions .............................................. 405
Considerations when Enabling ........................ 410
Syntax .............................................................. 405
Use with MPLAB IDE Tools ............................. 412