參數(shù)資料
型號(hào): PIC18F65K22-I/MRRSL
廠商: Microchip Technology
文件頁(yè)數(shù): 40/61頁(yè)
文件大小: 0K
描述: MCU PIC 32K FLASH MEM XLP 64QFN
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 40
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 64MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 托盤
P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
45 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
9.
Dynamic characteristics
[1]
Tcy(clk) = 1/fosc.
Table 45.
Dynamic characteristics
Over operating conditions: load capacitance for Port 0, ALE, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF
Tamb = 40 °C to +85 °C; VDD = 2.7 V to 5.5 V; VSS =0V[1]
Symbol
Parameter
Conditions
Min
Max
Unit
fosc
oscillator frequency
12-clock mode
0
40
MHz
6-clock mode
0
20
MHz
tLHLL
ALE pulse width
2Tcy(clk) 15
-
ns
tAVLL
address valid to ALE LOW time
Tcy(clk) 15
-
ns
tLLAX
address hold after ALE LOW time
Tcy(clk) 15
-
ns
tLLIV
ALE LOW to valid instruction in time
-
4Tcy(clk) 45
ns
tLLPL
ALE LOW to PSEN LOW time
Tcy(clk) 15
-
ns
tPLPH
PSEN pulse width
3Tcy(clk) 15
-
ns
tPLIV
PSEN LOW to valid instruction in time
-
3Tcy(clk) 55
ns
tPXIX
input instruction hold after PSEN time
0
-
ns
tPXIZ
input instruction oat after PSEN time
-
Tcy(clk) 20
ns
tPXAV
PSEN to address valid time
Tcy(clk) 8-
ns
tAVIV
address to valid instruction in time
-
5Tcy(clk) 60
ns
tPLAZ
PSEN LOW to address oat time
-
10
ns
tRLRH
RD LOW pulse width
6Tcy(clk) 30
-
ns
tWLWH
WR LOW pulse width
6Tcy(clk) 30
-
ns
tRLDV
RD LOW to valid data in time
-
5Tcy(clk) 50
ns
tRHDX
data hold after RD time
0
-
ns
tRHDZ
data oat after RD time
-
2Tcy(clk) 12
ns
tLLDV
ALE LOW to valid data in time
-
8Tcy(clk) 50
ns
tAVDV
address to valid data in time
-
9Tcy(clk) 75
ns
tLLWL
ALE LOW to RD or WR LOW time
3Tcy(clk) 15
3Tcy(clk) + 15
ns
tAVWL
address to RD or WR LOW time
4Tcy(clk) 30
-
ns
tWHQX
data hold after WR time
Tcy(clk) 20
-
ns
tQVWH
data output valid to WR HIGH time
7Tcy(clk) 50
-
ns
tRLAZ
RD LOW to address oat time
-
0
ns
tWHLH
RD or WR HIGH to ALE HIGH time
Tcy(clk) 15
Tcy(clk) + 15
ns
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