參數(shù)資料
型號: PIC18F65J50T-I/PT
廠商: Microchip Technology
文件頁數(shù): 17/61頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 16KX16 64TQFP
產品培訓模塊: Asynchronous Stimulus
PIC18 J Series MCU Overview
標準包裝: 1,200
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設備: 欠壓檢測/復位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 49
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 帶卷 (TR)
配用: AC162087-ND - HEADER MPLAB ICD2 18F87J50 68/84
MA180021-ND - MODULE PLUG-IN 18F87J50 FS USB
AC164327-ND - MODULE SKT FOR 64TQFP
其它名稱: PIC18F65J50T-I/PTTR
PIC18F87J50 FAMILY
DS39775C-page 24
2009 Microchip Technology Inc.
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/FLT0/INT0
RB0
FLT0
INT0
58
I/O
I
TTL
ST
Digital I/O.
ECCP1/2/3 Fault input.
External interrupt 0.
RB1/INT1/PMA4
RB1
INT1
PMA4
57
I/O
I
O
TTL
ST
Digital I/O.
External interrupt 1.
Parallel Master Port address.
RB2/INT2/PMA3
RB2
INT2
PMA3
56
I/O
I
O
TTL
ST
Digital I/O.
External interrupt 2.
Parallel Master Port address.
RB3/INT3/ECCP2/
P2A/PMA2
RB3
INT3
ECCP2(1)
P2A(1)
PMA2
55
I/O
I
I/O
O
TTL
ST
Digital I/O.
External interrupt 3.
Capture 2 input/Compare 2 output/PWM2 output.
ECCP2 PWM output A.
Parallel Master Port address.
RB4/KBI0/PMA1
RB4
KBI0
PMA1
54
I/O
I
I/O
TTL
Digital I/O.
Interrupt-on-change pin.
Parallel Master Port address.
RB5/KBI1/PMA0
RB5
KBI1
PMA0
53
I/O
I
I/O
TTL
Digital I/O.
Interrupt-on-change pin.
Parallel Master Port address.
RB6/KBI2/PGC
RB6
KBI2
PGC
52
I/O
I
I/O
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
47
I/O
I
I/O
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-4:
PIC18F8XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
80-TQFP
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1:
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (Extended Microcontroller
mode).
2: Default assignment for ECCP2/P2A for all devices in all operating modes (CCP2MX is set).
3: Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set).
4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode).
5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared).
6: Pin placement when PMPMX = 1.
7: Pin placement when PMPMX = 0.
8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
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