參數(shù)資料
型號: PIC18F65J50T-I/PT
廠商: Microchip Technology
文件頁數(shù): 14/61頁
文件大小: 0K
描述: IC PIC MCU FLASH 16KX16 64TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
PIC18 J Series MCU Overview
標(biāo)準(zhǔn)包裝: 1,200
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 49
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 帶卷 (TR)
配用: AC162087-ND - HEADER MPLAB ICD2 18F87J50 68/84
MA180021-ND - MODULE PLUG-IN 18F87J50 FS USB
AC164327-ND - MODULE SKT FOR 64TQFP
其它名稱: PIC18F65J50T-I/PTTR
2009 Microchip Technology Inc.
DS39775C-page 21
PIC18F87J50 FAMILY
PORTG is a bidirectional I/O port.
RG0/PMA8/ECCP3/P3A
RG0
PMA8
ECCP3
P3A
3
I/O
O
I/O
O
ST
Digital I/O.
Parallel Master Port address.
Capture 3 input/Compare 3 output/PWM3 output.
ECCP3 PWM output A.
RG1/PMA7/TX2/CK2
RG1
PMA7
TX2
CK2
4
I/O
O
I/O
ST
ST
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous transmit.
EUSART2 synchronous clock (see related RX2/DT2).
RG2/PMA6/RX2/DT2
RG2
PMA6
RX2
DT2
5
I/O
O
I
I/O
ST
ST
Digital I/O.
Parallel Master Port address.
EUSART2 asynchronous receive.
EUSART2 synchronous data (see related TX2/CK2).
RG3/PMCS1/CCP4/P3D
RG3
PMCS1
CCP4
P3D
6
I/O
O
I/O
O
ST
ST
Digital I/O.
Parallel Master Port chip select 1.
Capture 4 input/Compare 4 output/PWM4 output.
ECCP3 PWM output D.
RG4/PMCS2/CCP5/P1D
RG4
PMCS2
CCP5
P1D
8
I/O
O
I/O
O
ST
ST
Digital I/O.
Parallel Master Port chip select 2.
Capture 5 input/Compare 5 output/PWM5 output.
ECCP1 PWM output D.
VSS
9, 25, 41, 56
P
Ground reference for logic and I/O pins.
VDD
26, 38, 57
P
Positive supply for peripheral digital logic and I/O pins.
AVSS
20
P
Ground reference for analog modules.
AVDD
19
P
Positive supply for analog modules.
ENVREG
18
I
ST
Enable for on-chip voltage regulator.
VDDCORE/VCAP
VDDCORE
VCAP
10
P
Core logic power or external filter capacitor connection.
Positive supply for microcontroller core logic
(regulator disabled).
External filter capacitor connection (regulator
enabled).
VUSB
17
P
USB voltage input pin.
TABLE 1-3:
PIC18F6XJ5X PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
64-TQFP
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared.
3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function.
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