2007 Microchip Technology Inc.
Advance Information
DS41303B-page 55
PIC18F2XK20/4XK20
FIGURE 4-6:
SLOW RISE TIME (MCLR TIED TO V
DD
, V
DD
RISE > T
PWRT
)
FIGURE 4-7:
TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO V
DD
)
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V
5V
T
PWRT
T
OST
T
PWRT
T
OST
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
T
PLL
Note:
T
OST
= 1024 clock cycles.
T
PLL
≈
2 ms max. First three stages of the PWRT timer.
