
PIC18F2XK20/4XK20
DS41303B-page 118
Advance Information
2007 Microchip Technology Inc.
TABLE 10-1:
PORTA I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
I/O
Type
Description
RA0/AN0/C12IN0-
RA0
0
O
I
I
DIG
TTL
ANA
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
ADC input channel 0. Default input configuration on POR; does not
affect digital output.
Comparators C1 and C2 inverting input, channel 0. Analog select is
shared with ADC.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
ADC input channel 1. Default input configuration on POR; does not
affect digital output.
Comparators C1 and C2 inverting input, channel 1. Analog select is
shared with ADC.
LATA<2> data output; not affected by analog input. Disabled when
CV
REF
output enabled.
PORTA<2> data input. Disabled when analog functions enabled;
disabled when CV
REF
output enabled.
ADC input channel 2. Default input configuration on POR; not affected
by analog output.
Comparator C2 non-inverting input. Analog selection is shared with
ADC.
ADC and comparator voltage reference low input.
Comparator voltage reference output. Enabling this feature disables
digital I/O.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D input channel 3. Default input configuration on POR.
Comparator C1 non-inverting input. Analog selection is shared with
ADC.
ADC and comparator voltage reference high input.
LATA<4> data output.
PORTA<4> data input; default configuration on POR.
Timer0 clock input.
Comparator 1 output; takes priority over port data.
1
AN0
1
C12IN0-
1
I
ANA
RA1/AN1/C12IN1-
RA1
0
O
I
I
DIG
TTL
ANA
1
AN1
1
C12IN1-
1
I
ANA
RA2/AN2/C2IN+
V
REF
-/CV
REF
RA2
0
O
DIG
1
I
TTL
AN2
1
I
ANA
C2IN+
1
I
ANA
V
REF
-
CV
REF
1
I
ANA
ANA
x
O
RA3/AN3/C1IN+/
V
REF
+
RA3
0
O
I
I
I
DIG
TTL
ANA
ANA
1
AN3
C1IN+
1
1
V
REF
+
RA4
1
I
ANA
DIG
ST
ST
DIG
RA4/T0CKI/C1OUT
0
O
I
I
O
1
T0CKI
C1OUT
1
0
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
0
O
I
I
DIG
TTL
ANA
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D input channel 4. Default configuration on POR.
1
AN4
1
SS
1
I
I
TTL
ANA
DIG
DIG
TTL
Slave select input for SSP (MSSP module).
Low-Voltage Detect external trip point input.
Comparator 2 output; takes priority over port data.
LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes
only.
Main oscillator feedback output connection (XT, HS and LP modes).
System cycle clock output (F
OSC
/4) in RC, INTIO1 and EC Oscillator
modes.
HLVDIN
C2OUT
RA6
1
0
O
O
I
OSC2/CLKOUT/
RA6
0
1
OSC2
CLKOUT
x
O
O
ANA
DIG
x
Legend:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x
= Don’t care (TRIS bit does not affect port direction or is overridden for this option).