
2002 Microchip Technology Inc.
DS41159B-page 285
PIC18FXX8
ANDWF
Example:
Before Instruction
W
REG
After Instruction
W
REG
BC
AND W with f
Syntax:
Operands:
[
label
] ANDWF f [,d [,a]]
0
≤
f
≤
255
d
∈
[0,1]
a
∈
[0,1]
(W) .AND. (f)
→
dest
N, Z
Operation:
Status Affected:
Encoding:
Description:
0001
01da
ffff
ffff
The contents of W are AND’ed with
register 'f'. If 'd' is 0, the result is
stored in W. If 'd' is 1, the result is
stored back in register 'f' (default). If
‘a(chǎn)’ is 0, the Access Bank will be
selected. If ‘a(chǎn)’ is 1, the BSR will not
be overridden (default).
1
1
Words:
Cycles:
Q Cycle Activity:
Q1
Q2
Read
register ’f’
Q3
Q4
Decode
Process
Data
Write to
destination
ANDWF
REG, W
=
=
0x17
0xC2
=
=
0x02
0xC2
Branch if Carry
Syntax:
Operands:
Operation:
[
label
] BC n
-128
≤
n
≤
127
if carry bit is ’1’
(PC) + 2 + 2n
→
PC
None
Status Affected:
Encoding:
Description:
1110
0010
nnnn
nnnn
If the Carry bit is ’1’, then the
program will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
Words:
Cycles:
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
’n’
No
operation
Process
Data
No
operation
Write to PC
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
No
Decode
Read literal
’n’
Process
Data
operation
Example:
Before Instruction
PC
After Instruction
If Carry
HERE
BC
JUMP
=
address
(HERE)
=
=
=
=
1;
address
(JUMP)
0;
address
(HERE+2)
PC
If Carry
PC