2002 Microchip Technology Inc.
Preliminary
DS41159B-page 51
PIC18FXX8
IPR1
PIR1
PIE1
TRISE
(1)
TRISD
(1)
TRISC
TRISB
TRISA
(3)
LATE
(1)
PSPIP
PSPIF
PSPIE
IBF
Data Direction Control Register for PORTD
(1)
Data Direction Control Register for PORTC
Data Direction Control Register for PORTB
ADIP
ADIF
ADIE
OBF
RCIP
RCIF
RCIE
IBOV
TXIP
TXIF
TXIE
SSPIP
SSPIF
SSPIE
—
CCP1IP
CCP1IF
CCP1IE
Data Direction bits for PORTE
(1)
TMR2IP
TMR2IF
TMR2IE
TMR1IP
TMR1IF
TMR1IE
1111 1111
0000 0000
0000 0000
0000 -111
33, 88
33, 82
33, 85
33, 103
PSPMODE
1111 1111
1111 1111
1111 1111
33, 100
33, 98
33, 95
—
—
Data Direction Control Register for PORTA
—
—
--11 1111
---- -xxx
33, 93
33, 102
—
—
Read PORTE Data Latch, Write
PORTE Data Latch
(1)
LATD
(1)
LATC
LATB
LATA
(3)
PORTE
(1)
Read PORTD Data Latch, Write PORTD Data Latch
(1)
Read PORTC Data Latch, Write PORTC Data Latch
Read PORTB Data Latch, Write PORTB Data Latch
xxxx xxxx
xxxx xxxx
xxxx xxxx
33, 100
33, 98
33, 95
—
Read PORTA Data Latch, Write PORTA Data Latch
-xxx xxxx
33, 93
—
—
—
—
—
Read PORTE pins, Write PORTE
Data Latch
(1)
---- -000
33, 102
PORTD
(1)
PORTC
PORTB
PORTA
(3)
TXERRCNT
RXERRCNT
COMSTAT
CIOCON
BRGCON3
BRGCON2
BRGCON1
Read PORTD pins, Write PORTD Data Latch
(1)
Read PORTC pins, Write PORTC Data Latch
Read PORTB pins, Write PORTB Data Latch
xxxx xxxx
xxxx xxxx
xxxx xxxx
33, 100
33, 98
33, 95
—
Read PORTA pins, Write PORTA Data Latch
TEC6
TEC5
REC6
REC5
RXB0OVFL RXB1OVFL
—
—
—
WAKFIL
SEG2PHTS
SAM
SEG1PH2
SJW1
SJW0
-x0x 0000
0000 0000
0000 0000
0000 0000
--00 ----
33, 93
33, 207
33, 212
33, 203
33, 217
33, 217
33, 216
33, 215
TEC7
REC7
TEC4
REC4
TXBP
CANCAP
—
SEG1PH1
BRP4
TEC3
REC3
RXBP
—
—
SEG1PH0
BRP3
TEC2
REC2
TXWARN
—
SEG2PH2 SEG2PH1 SEG2PH0
-0-- -000
PRSEG2
PRSEG1
BRP2
BRP1
TEC1
REC1
RXWARN
—
TEC0
REC0
EWARN
—
TXBO
ENDRHI
—
PRSEG0
BRP0
0000 0000
0000 0000
BRP5
CANCON
CANSTAT
RXB0D7
RXB0D6
RXB0D5
RXB0D4
RXB0D3
RXB0D2
RXB0D1
RXB0D0
RXB0DLC
RXB0EIDL
RXB0EIDH
RXB0SIDL
RXB0SIDH
RXB0CON
Legend:
Note
REQOP2
OPMODE2
RXB0D77
RXB0D67
RXB0D57
RXB0D47
RXB0D37
RXB0D27
RXB0D17
RXB0D07
—
EID7
EID15
SID2
SID10
RXFUL
x
= unknown,
u
= unchanged, - = unimplemented,
q
= value depends on condition
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as
’
0
’
s.
Bit21 of the TBLPTRU allows access to the device configuration bits.
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read
‘
0
’
in all other Oscillator
modes.
REQOP1
OPMODE1
RXB0D76
RXB0D66
RXB0D56
RXB0D46
RXB0D36
RXB0D26
RXB0D16
RXB0D06
RXRTR
EID6
EID14
SID1
SID9
RXM1
REQOP0
OPMODE0
RXB0D75
RXB0D65
RXB0D55
RXB0D45
RXB0D35
RXB0D25
RXB0D15
RXB0D05
RB1
EID5
EID13
SID0
SID8
RXM0
ABAT
—
RXB0D74
RXB0D64
RXB0D54
RXB0D44
RXB0D34
RXB0D24
RXB0D14
RXB0D04
RB0
EID4
EID12
SRR
SID7
—
WIN2
ICODE2
RXB0D73
RXB0D63
RXB0D53
RXB0D43
RXB0D33
RXB0D23
RXB0D13
RXB0D03
DLC3
EID3
EID11
EXID
SID6
RXRTRRO RXB0DBEN
WIN1
ICODE1
RXB0D72
RXB0D62
RXB0D52
RXB0D42
RXB0D32
RXB0D22
RXB0D12
RXB0D02
DLC2
EID2
EID10
—
SID5
WIN0
ICODE0
RXB0D71
RXB0D61
RXB0D51
RXB0D41
RXB0D31
RXB0D21
RXB0D11
RXB0D01
DLC1
EID1
EID9
EID17
SID4
JTOFF
—
—
xxxx xxx-
xxx- xxx-
33, 199
33, 200
34, 211
34, 211
34, 211
34, 211
34, 211
34, 211
34, 211
34, 211
34, 211
34, 210
34, 210
34, 210
34, 209
34, 208
RXB0D70
xxxx xxxx
RXB0D60
xxxx xxxx
RXB0D50
xxxx xxxx
RXB0D40
xxxx xxxx
RXB0D30
xxxx xxxx
RXB0D20
xxxx xxxx
RXB0D10
xxxx xxxx
RXB0D00
xxxx xxxx
DLC0
-xxx xxxx
EID0
xxxx xxxx
EID8
xxxx xxxx
EID16
xxxx x-xx
SID3
xxxx xxxx
FILHIT0
000- 0000
TABLE 4-2:
REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
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