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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� PIC18F4585-I/ML
寤犲晢锛� Microchip Technology
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 280/322闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MCU FLASH 24KX16 44QFN
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 45
绯诲垪锛� PIC® 18F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 40MHz
閫ｉ€氭€э細 CAN锛孖²C锛孲PI锛孶ART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孒LVD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 36
绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 48KB锛�24K x 16锛�
绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 1K x 8
RAM 瀹归噺锛� 3.25K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4.2 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 11x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 44-VQFN 瑁搁湶鐒婄洡(p谩n)
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 645 (CN2011-ZH PDF)
閰嶇敤锛� XLT44QFN2-ND - SOCKET TRAN ICE 44QFN/40DIP
AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
I3-DB18F4680-ND - BOARD DAUGHTER ICEPIC3
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
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PIC18F2585/2680/4585/4680
DS39625C-page 58
Preliminary
2007 Microchip Technology Inc.
B2CON(6)
2585 2680 4585 4680
0000 0000
uuuu uuuu
B1D7(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B1D6(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B1D5(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B1D4(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B1D3(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B1D2(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B1D1(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B1D0(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B1DLC(6)
2585 2680 4585 4680
-xxx xxxx
-uuu uuuu
B1EIDL(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B1EIDH(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B1SIDL(6)
2585 2680 4585 4680
xxxx x-xx
uuuu u-uu
B1SIDH(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B1CON(6)
2585 2680 4585 4680
0000 0000
uuuu uuuu
B0D7(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0D6(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0D5(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0D4(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0D3(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0D2(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0D1(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0D0(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0DLC(6)
2585 2680 4585 4680
-xxx xxxx
-uuu uuuu
B0EIDL(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0EIDH(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0SIDL(6)
2585 2680 4585 4680
xxxx x-xx
uuuu u-uu
B0SIDH(6)
2585 2680 4585 4680
xxxx xxxx
uuuu uuuu
B0CON(6)
2585 2680 4585 4680
0000 0000
uuuu uuuu
TXBIE(6)
2585 2680 4585 4680
---0 00--
---u uu--
BIE0(6)
2585 2680 4585 4680
0000 0000
uuuu uuuu
TABLE 4-4:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET
Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as 鈥�0鈥�, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1:
One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3:
When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4:
See Table 4-3 for Reset value for specific condition.
5:
Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read 鈥�0鈥�.
6:
This register reads all 鈥�0鈥檚 until the ECAN technology is set up in Mode 1 or Mode 2.
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PIC18F4585T-I/ML 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 48KB 3328 RAM w/ECAN RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F4585T-I/PT 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 48KB 3328 RAM w/ECAN RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F458-E/L 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB 1536 RAM 34 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F458-E/P 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB 1536 RAM 34 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18F458-E/PT 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB 1536 RAM 34 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔(xi脿n)瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
鐧�(f膩)甯冪穵鎬ラ噰璩�(g貌u)锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�

閲囪臣(g貌u)闇€姹�

(鑻ュ彧閲囪臣(g貌u)涓€姊濆瀷铏�(h脿o)锛屽～瀵�(xi臎)涓€琛屽嵆鍙�)

鐧�(f膩)甯冩垚鍔�锛佹偍鍙互绻肩簩(x霉)鐧�(f膩)甯冮噰璩�(g貌u)銆備篃鍙互閫�(j矛n)鍏ユ垜鐨勫悗鑷�(t谩i)锛屾煡鐪嬪牨(b脿o)鍍�(ji脿)

鐧�(f膩)甯冩垚鍔燂紒鎮ㄥ彲浠ョ辜绾�(x霉)鐧�(f膩)甯冮噰璩�(g貌u)銆備篃鍙互閫�(j矛n)鍏ユ垜鐨勫悗鑷�(t谩i)锛屾煡鐪嬪牨(b脿o)鍍�(ji脿)

*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
娣诲姞鏇村閲囪臣(g貌u)

鎴戠殑鑱�(li谩n)绯绘柟寮�

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