- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3871 > PIC18F43K22-I/MV (Microchip Technology)MCU PIC 8KB FLASH 40QFN PDF資料下載
參數(shù)資料
| 型號(hào)： | PIC18F43K22-I/MV |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 48/71頁(yè) |
| 文件大小： | 0K |
| 描述： | MCU PIC 8KB FLASH 40QFN |
| 產(chǎn)品培訓(xùn)模塊： | 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 73 |
| 系列： | PIC® XLP™ 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 64MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，HLVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 35 |
| 程序存儲(chǔ)器容量： | 8KB（4K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 256 x 8 |
| RAM 容量： | 512 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 30x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-UFQFN 裸露焊盤 |
| 包裝： | 管件 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)當(dāng)前第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)
PIC18(L)F2X/4XK22
DS41412F-page 52
2010-2012 Microchip Technology Inc.
FIGURE 3-5:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
3.4.1
PRI_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC<3:0> Configuration bits. The OSTS bit
remains set (see Figure 3-6).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval TCSD is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wake-
up, the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 3-7).
3.4.2
SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the SOSC
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS<1:0> bits to ‘01’ and execute
SLEEP
. When the clock source is switched to the SOSC
oscillator, the primary oscillator is shut down, the OSTS
bit is cleared and the SOSCRUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the SOSC oscillator. After an interval
of TCSD following the wake event, the CPU begins exe-
cuting code being clocked by the SOSC oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the SOSC oscillator continues to run (see Figure 3-7).
FIGURE 3-6:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program
PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1
Q2 Q3 Q4 Q1 Q2
Clock
Counter
PC + 6
PC + 4
Q1 Q2 Q3 Q4
Wake Event
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
TOST(1)
TPLL(1)
OSTS bit set
PC + 2
Note:
The SOSC oscillator should already be
running
prior
to
entering
SEC_IDLE
mode. At least one of the secondary oscil-
lator enable bits (SOSCGO, T1SOSCEN,
T3SOSCEN or T5SOSCEN) must be set
when the SLEEP instruction is executed.
Otherwise, the main system clock will con-
tinue to operate in the previously selected
mode and the corresponding IDLE mode
will
be
entered
(i.e.,
PRI_IDLE
or
RC_IDLE).
Q1
Peripheral
Program
PC
PC + 2
OSC1
Q3
Q4
Q1
CPU Clock
Clock
Counter
Q2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PIC16C55A-04I/P | IC MCU OTP 512X12 28DIP |
| PIC18LF43K22-I/MV | MCU PIC 8KB FLASH 40UQFN |
| PIC16C622A-20I/P | IC MCU OTP 2KX14 COMP 18DIP |
| PIC18F84J11T-I/PT | IC PIC MCU FLASH 8KX16 80TQFP |
| PIC18F24K22-I/SP | IC PIC MCU 16KB FLASH 28SPDIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PIC18F43K22T-I/ML | 功能描述:8位微控制器 -MCU 8KB Flash 3968b RAM SERIAL EE IND RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC18F43K22T-I/MV | 功能描述:8位微控制器 -MCU 8KB FL 512b RAM8bit familynanoWatt XLP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC18F43K22T-I/PT | 功能描述:8位微控制器 -MCU 8KB Flash 3968b RAM SERIAL EE IND RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC18F4410-E/ML | 功能描述:8位微控制器 -MCU 16KB 768 RAM 36I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC18F4410-E/P | 功能描述:8位微控制器 -MCU 16KB 768 RAM 36I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。