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參數(shù)資料
| 型號： | PIC18F43K22-I/MV |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 22/71頁 |
| 文件大?。?/td> | 0K |
| 描述： | MCU PIC 8KB FLASH 40QFN |
| 產(chǎn)品培訓(xùn)模塊： | 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 73 |
| 系列： | PIC® XLP™ 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 64MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，HLVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 35 |
| 程序存儲器容量： | 8KB（4K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 256 x 8 |
| RAM 容量： | 512 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 30x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-UFQFN 裸露焊盤 |
| 包裝： | 管件 |
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2010-2012 Microchip Technology Inc.
DS41412E-page 29
PIC18(L)F2X/4XK22
2.2
Oscillator Control
The OSCCON, OSCCON2 and OSCTUNE registers
(Register 2-1 to Register 2-3) control several aspects
of the device clock’s operation, both in full-power
operation and in power-managed modes.
Main System Clock Selection (SCS)
Primary Oscillator Circuit Shutdown (PRISD)
Secondary Oscillator Enable (SOSCGO)
Primary Clock Frequency 4x multiplier (PLLEN)
Internal Frequency selection bits (IRCF, INTSRC)
Clock Status bits (OSTS, HFIOFS, MFIOFS,
LFIOFS. SOSCRUN, PLLRDY)
Power management selection (IDLEN)
2.2.1
MAIN SYSTEM CLOCK SELECTION
The System Clock Select bits, SCS<1:0>, select the
main clock source. The available clock sources are
Primary clock defined by the FOSC<3:0> bits of
CONFIG1H. The primary clock can be the primary
oscillator, an external clock, or the internal
oscillator block.
Secondary clock (secondary oscillator)
Internal oscillator block (HFINTOSC, MFINTOSC
and LFINTOSC).
The clock source changes immediately after one or
more of the bits is written to, following a brief clock
transition interval. The SCS bits are cleared to select
the primary clock on all forms of Reset.
2.2.2
INTERNAL FREQUENCY
SELECTION
The
Internal
Oscillator
Frequency
Select
bits
(IRCF<2:0>) select the frequency output of the internal
oscillator block. The choices are the LFINTOSC source
(31.25 kHz),
the
MFINTOSC
source
(31.25 kHz,
250 kHz or 500 kHz) and the HFINTOSC source
(16 MHz) or one of the frequencies derived from the
HFINTOSC postscaler (31.25 kHz to 8 MHz). If the
internal oscillator block is supplying the main clock,
changing the states of these bits will have an immedi-
ate change on the internal oscillator’s output. On
device Resets, the output frequency of the internal
oscillator is set to the default frequency of 1 MHz.
2.2.3
LOW FREQUENCY SELECTION
When a nominal output frequency of 31.25 kHz is
selected (IRCF<2:0> = 000), users may choose
which internal oscillator acts as the source. This is
done with the INTSRC bit of the OSCTUNE register
and MFIOSEL bit of the OSCCON2 register. See
Figure 2-2 and Register 2-1 for specific 31.25 kHz
selection. This option allows users to select a
31.25 kHz clock (MFINTOSC or HFINTOSC) that can
be tuned using the TUN<5:0> bits in OSCTUNE
register, while maintaining power savings with a very
low clock speed. LFINTOSC always remains the
clock source for features such as the Watchdog Timer
and the Fail-Safe Clock Monitor, regardless of the
setting of INTSRC and MFIOSEL bits
This option allows users to select the tunable and more
precise
HFINTOSC
as
a
clock
source,
while
maintaining power savings with a very low clock speed.
2.2.4
POWER MANAGEMENT
The IDLEN bit of the OSCCON register determines
whether the device goes into Sleep mode or one of the
Idle modes when the SLEEP instruction is executed.
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