參數(shù)資料
型號(hào): PIC18F24J11-I/SO
廠商: Microchip Technology
文件頁數(shù): 2/32頁
文件大小: 0K
描述: IC PIC MCU FLASH 16K 2V 28-SOIC
產(chǎn)品培訓(xùn)模塊: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 27
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 16KB(8K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2.15 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 656 (CN2011-ZH PDF)
配用: XLT28SO-1-ND - SOCKET TRANSITION 28SOIC 300MIL
AC164332-ND - MODULE SKT FOR 28SOIC 18F45J10
PIC18F2XJXX/4XJXX FAMILY
DS39687E-page 10
2009 Microchip Technology Inc.
3.1.2
ICSP ROW ERASE
It is possible to erase one row (1024 bytes of data),
provided
the
block
is
not
code-protected
or
erase/write-protected. Rows are located at static
boundaries beginning at program memory address
000000h, extending to the internal program memory
The Row Erase duration is internally timed. After the
WR bit in EECON1 is set, a NOP is issued, where the
4th PGC is held high for the duration of the Row Erase
time, P10.
The
code
sequence
to
Row
Erase
a
PIC18F2XJXX/4XJXX family device is shown in
Table 3-2. The flowchart shown in Figure 3-4 depicts the
logic
necessary
to
completely
erase
a
PIC18F2XJXX/4XJXX family device. The timing
diagram that details the “Row Erase” command and
parameter P10 is shown in Figure 3-6.
TABLE 3-2:
ERASE CODE MEMORY CODE SEQUENCE
FIGURE 3-3:
SET WR AND START ROW ERASE TIMING
Note 1: If the last row of program memory is
erased, bit 3 of CONFIG1H must also be
programmed as ‘0’.
2: The TBLPTR register can point at any
byte within the row intended for erase.
3: If code protection has been enabled,
ICSP Bulk Erase (all program memory
erased) operations can be used to dis-
able code protection. ICSP Row Erase
operations cannot be used to disable
code protection.
4-Bit
Command
Data Payload
Core Instruction
Step 1: Enable memory writes.
0000
84 A6
BSF
EECON1, WREN
Step 2: Point to first row in code memory.
0000
6A F8
6A F7
6A F6
CLRF
TBLPTRU
CLRF
TBLPTRH
CLRF
TBLPTRL
Step 3: Enable erase and erase single row.
0000
88 A6
82 A6
00 00
BSF
EECON1, FREE
BSF
EECON1, WR
NOP – hold PGC high for time P10.
Step 4: Repeat step 3, with Address Pointer incremented by 1024, until all rows are erased.
12
3
4
1
2
15 16
12
3
4
PGC
P5A
PGD
PGD = Input
0
00
0
34
6
5
P10
P5
Row-Erase Time
01
1
01
0
1
00
12
0
00
16-Bit
Data Payload
0
3
0
P5
4-Bit Command
16-Bit Data Payload
4-Bit Command
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